1comment "Processor Type"
2
3# Select CPU types depending on the architecture selected.  This selects
4# which CPUs we support in the kernel image, and the compiler instruction
5# optimiser behaviour.
6
7# ARM610
8config CPU_ARM610
9	bool "Support ARM610 processor" if ARCH_RPC
10	select CPU_32v3
11	select CPU_CACHE_V3
12	select CPU_CACHE_VIVT
13	select CPU_CP15_MMU
14	select CPU_COPY_V3 if MMU
15	select CPU_TLB_V3 if MMU
16	select CPU_PABRT_LEGACY
17	help
18	  The ARM610 is the successor to the ARM3 processor
19	  and was produced by VLSI Technology Inc.
20
21	  Say Y if you want support for the ARM610 processor.
22	  Otherwise, say N.
23
24# ARM7TDMI
25config CPU_ARM7TDMI
26	bool "Support ARM7TDMI processor"
27	depends on !MMU
28	select CPU_32v4T
29	select CPU_ABRT_LV4T
30	select CPU_PABRT_LEGACY
31	select CPU_CACHE_V4
32	help
33	  A 32-bit RISC microprocessor based on the ARM7 processor core
34	  which has no memory control unit and cache.
35
36	  Say Y if you want support for the ARM7TDMI processor.
37	  Otherwise, say N.
38
39# ARM710
40config CPU_ARM710
41	bool "Support ARM710 processor" if ARCH_RPC
42	select CPU_32v3
43	select CPU_CACHE_V3
44	select CPU_CACHE_VIVT
45	select CPU_CP15_MMU
46	select CPU_COPY_V3 if MMU
47	select CPU_TLB_V3 if MMU
48	select CPU_PABRT_LEGACY
49	help
50	  A 32-bit RISC microprocessor based on the ARM7 processor core
51	  designed by Advanced RISC Machines Ltd. The ARM710 is the
52	  successor to the ARM610 processor. It was released in
53	  July 1994 by VLSI Technology Inc.
54
55	  Say Y if you want support for the ARM710 processor.
56	  Otherwise, say N.
57
58# ARM720T
59config CPU_ARM720T
60	bool "Support ARM720T processor" if ARCH_INTEGRATOR
61	select CPU_32v4T
62	select CPU_ABRT_LV4T
63	select CPU_PABRT_LEGACY
64	select CPU_CACHE_V4
65	select CPU_CACHE_VIVT
66	select CPU_CP15_MMU
67	select CPU_COPY_V4WT if MMU
68	select CPU_TLB_V4WT if MMU
69	help
70	  A 32-bit RISC processor with 8kByte Cache, Write Buffer and
71	  MMU built around an ARM7TDMI core.
72
73	  Say Y if you want support for the ARM720T processor.
74	  Otherwise, say N.
75
76# ARM740T
77config CPU_ARM740T
78	bool "Support ARM740T processor" if ARCH_INTEGRATOR
79	depends on !MMU
80	select CPU_32v4T
81	select CPU_ABRT_LV4T
82	select CPU_PABRT_LEGACY
83	select CPU_CACHE_V3	# although the core is v4t
84	select CPU_CP15_MPU
85	help
86	  A 32-bit RISC processor with 8KB cache or 4KB variants,
87	  write buffer and MPU(Protection Unit) built around
88	  an ARM7TDMI core.
89
90	  Say Y if you want support for the ARM740T processor.
91	  Otherwise, say N.
92
93# ARM9TDMI
94config CPU_ARM9TDMI
95	bool "Support ARM9TDMI processor"
96	depends on !MMU
97	select CPU_32v4T
98	select CPU_ABRT_NOMMU
99	select CPU_PABRT_LEGACY
100	select CPU_CACHE_V4
101	help
102	  A 32-bit RISC microprocessor based on the ARM9 processor core
103	  which has no memory control unit and cache.
104
105	  Say Y if you want support for the ARM9TDMI processor.
106	  Otherwise, say N.
107
108# ARM920T
109config CPU_ARM920T
110	bool "Support ARM920T processor" if ARCH_INTEGRATOR
111	select CPU_32v4T
112	select CPU_ABRT_EV4T
113	select CPU_PABRT_LEGACY
114	select CPU_CACHE_V4WT
115	select CPU_CACHE_VIVT
116	select CPU_CP15_MMU
117	select CPU_COPY_V4WB if MMU
118	select CPU_TLB_V4WBI if MMU
119	help
120	  The ARM920T is licensed to be produced by numerous vendors,
121	  and is used in the Cirrus EP93xx and the Samsung S3C2410.
122
123	  Say Y if you want support for the ARM920T processor.
124	  Otherwise, say N.
125
126# ARM922T
127config CPU_ARM922T
128	bool "Support ARM922T processor" if ARCH_INTEGRATOR
129	select CPU_32v4T
130	select CPU_ABRT_EV4T
131	select CPU_PABRT_LEGACY
132	select CPU_CACHE_V4WT
133	select CPU_CACHE_VIVT
134	select CPU_CP15_MMU
135	select CPU_COPY_V4WB if MMU
136	select CPU_TLB_V4WBI if MMU
137	help
138	  The ARM922T is a version of the ARM920T, but with smaller
139	  instruction and data caches. It is used in Altera's
140	  Excalibur XA device family and Micrel's KS8695 Centaur.
141
142	  Say Y if you want support for the ARM922T processor.
143	  Otherwise, say N.
144
145# ARM925T
146config CPU_ARM925T
147 	bool "Support ARM925T processor" if ARCH_OMAP1
148	select CPU_32v4T
149	select CPU_ABRT_EV4T
150	select CPU_PABRT_LEGACY
151	select CPU_CACHE_V4WT
152	select CPU_CACHE_VIVT
153	select CPU_CP15_MMU
154	select CPU_COPY_V4WB if MMU
155	select CPU_TLB_V4WBI if MMU
156 	help
157 	  The ARM925T is a mix between the ARM920T and ARM926T, but with
158	  different instruction and data caches. It is used in TI's OMAP
159 	  device family.
160
161 	  Say Y if you want support for the ARM925T processor.
162 	  Otherwise, say N.
163
164# ARM926T
165config CPU_ARM926T
166	bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
167	select CPU_32v5
168	select CPU_ABRT_EV5TJ
169	select CPU_PABRT_LEGACY
170	select CPU_CACHE_VIVT
171	select CPU_CP15_MMU
172	select CPU_COPY_V4WB if MMU
173	select CPU_TLB_V4WBI if MMU
174	help
175	  This is a variant of the ARM920.  It has slightly different
176	  instruction sequences for cache and TLB operations.  Curiously,
177	  there is no documentation on it at the ARM corporate website.
178
179	  Say Y if you want support for the ARM926T processor.
180	  Otherwise, say N.
181
182# FA526
183config CPU_FA526
184	bool
185	select CPU_32v4
186	select CPU_ABRT_EV4
187	select CPU_PABRT_LEGACY
188	select CPU_CACHE_VIVT
189	select CPU_CP15_MMU
190	select CPU_CACHE_FA
191	select CPU_COPY_FA if MMU
192	select CPU_TLB_FA if MMU
193	help
194	  The FA526 is a version of the ARMv4 compatible processor with
195	  Branch Target Buffer, Unified TLB and cache line size 16.
196
197	  Say Y if you want support for the FA526 processor.
198	  Otherwise, say N.
199
200# ARM940T
201config CPU_ARM940T
202	bool "Support ARM940T processor" if ARCH_INTEGRATOR
203	depends on !MMU
204	select CPU_32v4T
205	select CPU_ABRT_NOMMU
206	select CPU_PABRT_LEGACY
207	select CPU_CACHE_VIVT
208	select CPU_CP15_MPU
209	help
210	  ARM940T is a member of the ARM9TDMI family of general-
211	  purpose microprocessors with MPU and separate 4KB
212	  instruction and 4KB data cases, each with a 4-word line
213	  length.
214
215	  Say Y if you want support for the ARM940T processor.
216	  Otherwise, say N.
217
218# ARM946E-S
219config CPU_ARM946E
220	bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
221	depends on !MMU
222	select CPU_32v5
223	select CPU_ABRT_NOMMU
224	select CPU_PABRT_LEGACY
225	select CPU_CACHE_VIVT
226	select CPU_CP15_MPU
227	help
228	  ARM946E-S is a member of the ARM9E-S family of high-
229	  performance, 32-bit system-on-chip processor solutions.
230	  The TCM and ARMv5TE 32-bit instruction set is supported.
231
232	  Say Y if you want support for the ARM946E-S processor.
233	  Otherwise, say N.
234
235# ARM1020 - needs validating
236config CPU_ARM1020
237	bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
238	select CPU_32v5
239	select CPU_ABRT_EV4T
240	select CPU_PABRT_LEGACY
241	select CPU_CACHE_V4WT
242	select CPU_CACHE_VIVT
243	select CPU_CP15_MMU
244	select CPU_COPY_V4WB if MMU
245	select CPU_TLB_V4WBI if MMU
246	help
247	  The ARM1020 is the 32K cached version of the ARM10 processor,
248	  with an addition of a floating-point unit.
249
250	  Say Y if you want support for the ARM1020 processor.
251	  Otherwise, say N.
252
253# ARM1020E - needs validating
254config CPU_ARM1020E
255	bool "Support ARM1020E processor" if ARCH_INTEGRATOR
256	select CPU_32v5
257	select CPU_ABRT_EV4T
258	select CPU_PABRT_LEGACY
259	select CPU_CACHE_V4WT
260	select CPU_CACHE_VIVT
261	select CPU_CP15_MMU
262	select CPU_COPY_V4WB if MMU
263	select CPU_TLB_V4WBI if MMU
264	depends on n
265
266# ARM1022E
267config CPU_ARM1022
268	bool "Support ARM1022E processor" if ARCH_INTEGRATOR
269	select CPU_32v5
270	select CPU_ABRT_EV4T
271	select CPU_PABRT_LEGACY
272	select CPU_CACHE_VIVT
273	select CPU_CP15_MMU
274	select CPU_COPY_V4WB if MMU # can probably do better
275	select CPU_TLB_V4WBI if MMU
276	help
277	  The ARM1022E is an implementation of the ARMv5TE architecture
278	  based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
279	  embedded trace macrocell, and a floating-point unit.
280
281	  Say Y if you want support for the ARM1022E processor.
282	  Otherwise, say N.
283
284# ARM1026EJ-S
285config CPU_ARM1026
286	bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
287	select CPU_32v5
288	select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
289	select CPU_PABRT_LEGACY
290	select CPU_CACHE_VIVT
291	select CPU_CP15_MMU
292	select CPU_COPY_V4WB if MMU # can probably do better
293	select CPU_TLB_V4WBI if MMU
294	help
295	  The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
296	  based upon the ARM10 integer core.
297
298	  Say Y if you want support for the ARM1026EJ-S processor.
299	  Otherwise, say N.
300
301# SA110
302config CPU_SA110
303	bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
304	select CPU_32v3 if ARCH_RPC
305	select CPU_32v4 if !ARCH_RPC
306	select CPU_ABRT_EV4
307	select CPU_PABRT_LEGACY
308	select CPU_CACHE_V4WB
309	select CPU_CACHE_VIVT
310	select CPU_CP15_MMU
311	select CPU_COPY_V4WB if MMU
312	select CPU_TLB_V4WB if MMU
313	help
314	  The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
315	  is available at five speeds ranging from 100 MHz to 233 MHz.
316	  More information is available at
317	  <http://developer.intel.com/design/strong/sa110.htm>.
318
319	  Say Y if you want support for the SA-110 processor.
320	  Otherwise, say N.
321
322# SA1100
323config CPU_SA1100
324	bool
325	select CPU_32v4
326	select CPU_ABRT_EV4
327	select CPU_PABRT_LEGACY
328	select CPU_CACHE_V4WB
329	select CPU_CACHE_VIVT
330	select CPU_CP15_MMU
331	select CPU_TLB_V4WB if MMU
332
333# XScale
334config CPU_XSCALE
335	bool
336	select CPU_32v5
337	select CPU_ABRT_EV5T
338	select CPU_PABRT_LEGACY
339	select CPU_CACHE_VIVT
340	select CPU_CP15_MMU
341	select CPU_TLB_V4WBI if MMU
342
343# XScale Core Version 3
344config CPU_XSC3
345	bool
346	select CPU_32v5
347	select CPU_ABRT_EV5T
348	select CPU_PABRT_LEGACY
349	select CPU_CACHE_VIVT
350	select CPU_CP15_MMU
351	select CPU_TLB_V4WBI if MMU
352	select IO_36
353
354# Marvell PJ1 (Mohawk)
355config CPU_MOHAWK
356	bool
357	select CPU_32v5
358	select CPU_ABRT_EV5T
359	select CPU_PABRT_LEGACY
360	select CPU_CACHE_VIVT
361	select CPU_CP15_MMU
362	select CPU_TLB_V4WBI if MMU
363	select CPU_COPY_V4WB if MMU
364
365# Feroceon
366config CPU_FEROCEON
367	bool
368	select CPU_32v5
369	select CPU_ABRT_EV5T
370	select CPU_PABRT_LEGACY
371	select CPU_CACHE_VIVT
372	select CPU_CP15_MMU
373	select CPU_COPY_FEROCEON if MMU
374	select CPU_TLB_FEROCEON if MMU
375
376config CPU_FEROCEON_OLD_ID
377	bool "Accept early Feroceon cores with an ARM926 ID"
378	depends on CPU_FEROCEON && !CPU_ARM926T
379	default y
380	help
381	  This enables the usage of some old Feroceon cores
382	  for which the CPU ID is equal to the ARM926 ID.
383	  Relevant for Feroceon-1850 and early Feroceon-2850.
384
385# Marvell PJ4
386config CPU_PJ4
387	bool
388	select CPU_V7
389	select ARM_THUMBEE
390
391# ARMv6
392config CPU_V6
393	bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
394	select CPU_32v6
395	select CPU_ABRT_EV6
396	select CPU_PABRT_V6
397	select CPU_CACHE_V6
398	select CPU_CACHE_VIPT
399	select CPU_CP15_MMU
400	select CPU_HAS_ASID if MMU
401	select CPU_COPY_V6 if MMU
402	select CPU_TLB_V6 if MMU
403
404# ARMv6k
405config CPU_V6K
406	bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
407	select CPU_32v6
408	select CPU_32v6K
409	select CPU_ABRT_EV6
410	select CPU_PABRT_V6
411	select CPU_CACHE_V6
412	select CPU_CACHE_VIPT
413	select CPU_CP15_MMU
414	select CPU_HAS_ASID if MMU
415	select CPU_COPY_V6 if MMU
416	select CPU_TLB_V6 if MMU
417
418# ARMv7
419config CPU_V7
420	bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
421	select CPU_32v6K
422	select CPU_32v7
423	select CPU_ABRT_EV7
424	select CPU_PABRT_V7
425	select CPU_CACHE_V7
426	select CPU_CACHE_VIPT
427	select CPU_CP15_MMU
428	select CPU_HAS_ASID if MMU
429	select CPU_COPY_V6 if MMU
430	select CPU_TLB_V7 if MMU
431
432# Figure out what processor architecture version we should be using.
433# This defines the compiler instruction set which depends on the machine type.
434config CPU_32v3
435	bool
436	select TLS_REG_EMUL if SMP || !MMU
437	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
438	select CPU_USE_DOMAINS if MMU
439
440config CPU_32v4
441	bool
442	select TLS_REG_EMUL if SMP || !MMU
443	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444	select CPU_USE_DOMAINS if MMU
445
446config CPU_32v4T
447	bool
448	select TLS_REG_EMUL if SMP || !MMU
449	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
450	select CPU_USE_DOMAINS if MMU
451
452config CPU_32v5
453	bool
454	select TLS_REG_EMUL if SMP || !MMU
455	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
456	select CPU_USE_DOMAINS if MMU
457
458config CPU_32v6
459	bool
460	select TLS_REG_EMUL if !CPU_32v6K && !MMU
461	select CPU_USE_DOMAINS if CPU_V6 && MMU
462
463config CPU_32v6K
464	bool
465
466config CPU_32v7
467	bool
468
469# The abort model
470config CPU_ABRT_NOMMU
471	bool
472
473config CPU_ABRT_EV4
474	bool
475
476config CPU_ABRT_EV4T
477	bool
478
479config CPU_ABRT_LV4T
480	bool
481
482config CPU_ABRT_EV5T
483	bool
484
485config CPU_ABRT_EV5TJ
486	bool
487
488config CPU_ABRT_EV6
489	bool
490
491config CPU_ABRT_EV7
492	bool
493
494config CPU_PABRT_LEGACY
495	bool
496
497config CPU_PABRT_V6
498	bool
499
500config CPU_PABRT_V7
501	bool
502
503# The cache model
504config CPU_CACHE_V3
505	bool
506
507config CPU_CACHE_V4
508	bool
509
510config CPU_CACHE_V4WT
511	bool
512
513config CPU_CACHE_V4WB
514	bool
515
516config CPU_CACHE_V6
517	bool
518
519config CPU_CACHE_V7
520	bool
521
522config CPU_CACHE_VIVT
523	bool
524
525config CPU_CACHE_VIPT
526	bool
527
528config CPU_CACHE_FA
529	bool
530
531if MMU
532# The copy-page model
533config CPU_COPY_V3
534	bool
535
536config CPU_COPY_V4WT
537	bool
538
539config CPU_COPY_V4WB
540	bool
541
542config CPU_COPY_FEROCEON
543	bool
544
545config CPU_COPY_FA
546	bool
547
548config CPU_COPY_V6
549	bool
550
551# This selects the TLB model
552config CPU_TLB_V3
553	bool
554	help
555	  ARM Architecture Version 3 TLB.
556
557config CPU_TLB_V4WT
558	bool
559	help
560	  ARM Architecture Version 4 TLB with writethrough cache.
561
562config CPU_TLB_V4WB
563	bool
564	help
565	  ARM Architecture Version 4 TLB with writeback cache.
566
567config CPU_TLB_V4WBI
568	bool
569	help
570	  ARM Architecture Version 4 TLB with writeback cache and invalidate
571	  instruction cache entry.
572
573config CPU_TLB_FEROCEON
574	bool
575	help
576	  Feroceon TLB (v4wbi with non-outer-cachable page table walks).
577
578config CPU_TLB_FA
579	bool
580	help
581	  Faraday ARM FA526 architecture, unified TLB with writeback cache
582	  and invalidate instruction cache entry. Branch target buffer is
583	  also supported.
584
585config CPU_TLB_V6
586	bool
587
588config CPU_TLB_V7
589	bool
590
591config VERIFY_PERMISSION_FAULT
592	bool
593endif
594
595config CPU_HAS_ASID
596	bool
597	help
598	  This indicates whether the CPU has the ASID register; used to
599	  tag TLB and possibly cache entries.
600
601config CPU_CP15
602	bool
603	help
604	  Processor has the CP15 register.
605
606config CPU_CP15_MMU
607	bool
608	select CPU_CP15
609	help
610	  Processor has the CP15 register, which has MMU related registers.
611
612config CPU_CP15_MPU
613	bool
614	select CPU_CP15
615	help
616	  Processor has the CP15 register, which has MPU related registers.
617
618config CPU_USE_DOMAINS
619	bool
620	help
621	  This option enables or disables the use of domain switching
622	  via the set_fs() function.
623
624#
625# CPU supports 36-bit I/O
626#
627config IO_36
628	bool
629
630comment "Processor Features"
631
632config ARM_LPAE
633	bool "Support for the Large Physical Address Extension"
634	depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
635		!CPU_32v4 && !CPU_32v3
636	help
637	  Say Y if you have an ARMv7 processor supporting the LPAE page
638	  table format and you would like to access memory beyond the
639	  4GB limit. The resulting kernel image will not run on
640	  processors without the LPA extension.
641
642	  If unsure, say N.
643
644config ARCH_PHYS_ADDR_T_64BIT
645	def_bool ARM_LPAE
646
647config ARCH_DMA_ADDR_T_64BIT
648	bool
649
650config ARM_THUMB
651	bool "Support Thumb user binaries"
652	depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
653	default y
654	help
655	  Say Y if you want to include kernel support for running user space
656	  Thumb binaries.
657
658	  The Thumb instruction set is a compressed form of the standard ARM
659	  instruction set resulting in smaller binaries at the expense of
660	  slightly less efficient code.
661
662	  If you don't know what this all is, saying Y is a safe choice.
663
664config ARM_THUMBEE
665	bool "Enable ThumbEE CPU extension"
666	depends on CPU_V7
667	help
668	  Say Y here if you have a CPU with the ThumbEE extension and code to
669	  make use of it. Say N for code that can run on CPUs without ThumbEE.
670
671config SWP_EMULATE
672	bool "Emulate SWP/SWPB instructions"
673	depends on !CPU_USE_DOMAINS && CPU_V7
674	select HAVE_PROC_CPU if PROC_FS
675	default y if SMP
676	help
677	  ARMv6 architecture deprecates use of the SWP/SWPB instructions.
678	  ARMv7 multiprocessing extensions introduce the ability to disable
679	  these instructions, triggering an undefined instruction exception
680	  when executed. Say Y here to enable software emulation of these
681	  instructions for userspace (not kernel) using LDREX/STREX.
682	  Also creates /proc/cpu/swp_emulation for statistics.
683
684	  In some older versions of glibc [<=2.8] SWP is used during futex
685	  trylock() operations with the assumption that the code will not
686	  be preempted. This invalid assumption may be more likely to fail
687	  with SWP emulation enabled, leading to deadlock of the user
688	  application.
689
690	  NOTE: when accessing uncached shared regions, LDREX/STREX rely
691	  on an external transaction monitoring block called a global
692	  monitor to maintain update atomicity. If your system does not
693	  implement a global monitor, this option can cause programs that
694	  perform SWP operations to uncached memory to deadlock.
695
696	  If unsure, say Y.
697
698config CPU_BIG_ENDIAN
699	bool "Build big-endian kernel"
700	depends on ARCH_SUPPORTS_BIG_ENDIAN
701	help
702	  Say Y if you plan on running a kernel in big-endian mode.
703	  Note that your board must be properly built and your board
704	  port must properly enable any big-endian related features
705	  of your chipset/board/processor.
706
707config CPU_ENDIAN_BE8
708	bool
709	depends on CPU_BIG_ENDIAN
710	default CPU_V6 || CPU_V6K || CPU_V7
711	help
712	  Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
713
714config CPU_ENDIAN_BE32
715	bool
716	depends on CPU_BIG_ENDIAN
717	default !CPU_ENDIAN_BE8
718	help
719	  Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
720
721config CPU_HIGH_VECTOR
722	depends on !MMU && CPU_CP15 && !CPU_ARM740T
723	bool "Select the High exception vector"
724	help
725	  Say Y here to select high exception vector(0xFFFF0000~).
726	  The exception vector can vary depending on the platform
727	  design in nommu mode. If your platform needs to select
728	  high exception vector, say Y.
729	  Otherwise or if you are unsure, say N, and the low exception
730	  vector (0x00000000~) will be used.
731
732config CPU_ICACHE_DISABLE
733	bool "Disable I-Cache (I-bit)"
734	depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
735	help
736	  Say Y here to disable the processor instruction cache. Unless
737	  you have a reason not to or are unsure, say N.
738
739config CPU_DCACHE_DISABLE
740	bool "Disable D-Cache (C-bit)"
741	depends on CPU_CP15
742	help
743	  Say Y here to disable the processor data cache. Unless
744	  you have a reason not to or are unsure, say N.
745
746config CPU_DCACHE_SIZE
747	hex
748	depends on CPU_ARM740T || CPU_ARM946E
749	default 0x00001000 if CPU_ARM740T
750	default 0x00002000 # default size for ARM946E-S
751	help
752	  Some cores are synthesizable to have various sized cache. For
753	  ARM946E-S case, it can vary from 0KB to 1MB.
754	  To support such cache operations, it is efficient to know the size
755	  before compile time.
756	  If your SoC is configured to have a different size, define the value
757	  here with proper conditions.
758
759config CPU_DCACHE_WRITETHROUGH
760	bool "Force write through D-cache"
761	depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
762	default y if CPU_ARM925T
763	help
764	  Say Y here to use the data cache in writethrough mode. Unless you
765	  specifically require this or are unsure, say N.
766
767config CPU_CACHE_ROUND_ROBIN
768	bool "Round robin I and D cache replacement algorithm"
769	depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
770	help
771	  Say Y here to use the predictable round-robin cache replacement
772	  policy.  Unless you specifically require this or are unsure, say N.
773
774config CPU_BPREDICT_DISABLE
775	bool "Disable branch prediction"
776	depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
777	help
778	  Say Y here to disable branch prediction.  If unsure, say N.
779
780config TLS_REG_EMUL
781	bool
782	help
783	  An SMP system using a pre-ARMv6 processor (there are apparently
784	  a few prototypes like that in existence) and therefore access to
785	  that required register must be emulated.
786
787config NEEDS_SYSCALL_FOR_CMPXCHG
788	bool
789	help
790	  SMP on a pre-ARMv6 processor?  Well OK then.
791	  Forget about fast user space cmpxchg support.
792	  It is just not possible.
793
794config DMA_CACHE_RWFO
795	bool "Enable read/write for ownership DMA cache maintenance"
796	depends on CPU_V6K && SMP
797	default y
798	help
799	  The Snoop Control Unit on ARM11MPCore does not detect the
800	  cache maintenance operations and the dma_{map,unmap}_area()
801	  functions may leave stale cache entries on other CPUs. By
802	  enabling this option, Read or Write For Ownership in the ARMv6
803	  DMA cache maintenance functions is performed. These LDR/STR
804	  instructions change the cache line state to shared or modified
805	  so that the cache operation has the desired effect.
806
807	  Note that the workaround is only valid on processors that do
808	  not perform speculative loads into the D-cache. For such
809	  processors, if cache maintenance operations are not broadcast
810	  in hardware, other workarounds are needed (e.g. cache
811	  maintenance broadcasting in software via FIQ).
812
813config OUTER_CACHE
814	bool
815
816config OUTER_CACHE_SYNC
817	bool
818	help
819	  The outer cache has a outer_cache_fns.sync function pointer
820	  that can be used to drain the write buffer of the outer cache.
821
822config CACHE_FEROCEON_L2
823	bool "Enable the Feroceon L2 cache controller"
824	depends on ARCH_KIRKWOOD || ARCH_MV78XX0
825	default y
826	select OUTER_CACHE
827	help
828	  This option enables the Feroceon L2 cache controller.
829
830config CACHE_FEROCEON_L2_WRITETHROUGH
831	bool "Force Feroceon L2 cache write through"
832	depends on CACHE_FEROCEON_L2
833	help
834	  Say Y here to use the Feroceon L2 cache in writethrough mode.
835	  Unless you specifically require this, say N for writeback mode.
836
837config MIGHT_HAVE_CACHE_L2X0
838	bool
839	help
840	  This option should be selected by machines which have a L2x0
841	  or PL310 cache controller, but where its use is optional.
842
843	  The only effect of this option is to make CACHE_L2X0 and
844	  related options available to the user for configuration.
845
846	  Boards or SoCs which always require the cache controller
847	  support to be present should select CACHE_L2X0 directly
848	  instead of this option, thus preventing the user from
849	  inadvertently configuring a broken kernel.
850
851config CACHE_L2X0
852	bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
853	default MIGHT_HAVE_CACHE_L2X0
854	select OUTER_CACHE
855	select OUTER_CACHE_SYNC
856	help
857	  This option enables the L2x0 PrimeCell.
858
859config CACHE_PL310
860	bool
861	depends on CACHE_L2X0
862	default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
863	help
864	  This option enables optimisations for the PL310 cache
865	  controller.
866
867config CACHE_TAUROS2
868	bool "Enable the Tauros2 L2 cache controller"
869	depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
870	default y
871	select OUTER_CACHE
872	help
873	  This option enables the Tauros2 L2 cache controller (as
874	  found on PJ1/PJ4).
875
876config CACHE_XSC3L2
877	bool "Enable the L2 cache on XScale3"
878	depends on CPU_XSC3
879	default y
880	select OUTER_CACHE
881	help
882	  This option enables the L2 cache on XScale3.
883
884config ARM_L1_CACHE_SHIFT_6
885	bool
886	default y if CPU_V7
887	help
888	  Setting ARM L1 cache line size to 64 Bytes.
889
890config ARM_L1_CACHE_SHIFT
891	int
892	default 6 if ARM_L1_CACHE_SHIFT_6
893	default 5
894
895config ARM_DMA_MEM_BUFFERABLE
896	bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
897	depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
898		     MACH_REALVIEW_PB11MP)
899	default y if CPU_V6 || CPU_V6K || CPU_V7
900	help
901	  Historically, the kernel has used strongly ordered mappings to
902	  provide DMA coherent memory.  With the advent of ARMv7, mapping
903	  memory with differing types results in unpredictable behaviour,
904	  so on these CPUs, this option is forced on.
905
906	  Multiple mappings with differing attributes is also unpredictable
907	  on ARMv6 CPUs, but since they do not have aggressive speculative
908	  prefetch, no harm appears to occur.
909
910	  However, drivers may be missing the necessary barriers for ARMv6,
911	  and therefore turning this on may result in unpredictable driver
912	  behaviour.  Therefore, we offer this as an option.
913
914	  You are recommended say 'Y' here and debug any affected drivers.
915
916config ARCH_HAS_BARRIERS
917	bool
918	help
919	  This option allows the use of custom mandatory barriers
920	  included via the mach/barriers.h file.
921