1/*
2 * arch/arm/mach-s3c2410/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for S3C2410-based platforms
5 *
6 * This file is licensed under  the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9*/
10
11/* We have a problem that the INTOFFSET register does not always
12 * show one interrupt. Occasionally we get two interrupts through
13 * the prioritiser, and this causes the INTOFFSET register to show
14 * what looks like the logical-or of the two interrupt numbers.
15 *
16 * Thanks to Klaus, Shannon, et al for helping to debug this problem
17*/
18
19#define INTPND		(0x10)
20#define INTOFFSET	(0x14)
21
22#include <mach/hardware.h>
23#include <asm/irq.h>
24
25	.macro  get_irqnr_preamble, base, tmp
26	.endm
27
28	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
29
30		mov	\base, #S3C24XX_VA_IRQ
31
32		@@ try the interrupt offset register, since it is there
33
34		ldr	\irqstat, [\base, #INTPND ]
35		teq	\irqstat, #0
36		beq	1002f
37		ldr	\irqnr, [\base, #INTOFFSET ]
38		mov	\tmp, #1
39		tst	\irqstat, \tmp, lsl \irqnr
40		bne	1001f
41
42		@@ the number specified is not a valid irq, so try
43		@@ and work it out for ourselves
44
45		mov	\irqnr, #0		@@ start here
46
47		@@ work out which irq (if any) we got
48
49		movs	\tmp, \irqstat, lsl#16
50		addeq	\irqnr, \irqnr, #16
51		moveq	\irqstat, \irqstat, lsr#16
52		tst	\irqstat, #0xff
53		addeq	\irqnr, \irqnr, #8
54		moveq	\irqstat, \irqstat, lsr#8
55		tst	\irqstat, #0xf
56		addeq	\irqnr, \irqnr, #4
57		moveq	\irqstat, \irqstat, lsr#4
58		tst	\irqstat, #0x3
59		addeq	\irqnr, \irqnr, #2
60		moveq	\irqstat, \irqstat, lsr#2
61		tst	\irqstat, #0x1
62		addeq	\irqnr, \irqnr, #1
63
64		@@ we have the value
651001:
66		adds	\irqnr, \irqnr, #IRQ_EINT0
671002:
68		@@ exit here, Z flag unset if IRQ
69
70	.endm
71