1 /*
2 * arch/arm/mach-orion5x/common.c
3 *
4 * Core functions for Marvell Orion 5x SoCs
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/serial_8250.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/ata_platform.h>
20 #include <linux/delay.h>
21 #include <net/dsa.h>
22 #include <asm/page.h>
23 #include <asm/setup.h>
24 #include <asm/system_misc.h>
25 #include <asm/timex.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/time.h>
29 #include <mach/bridge-regs.h>
30 #include <mach/hardware.h>
31 #include <mach/orion5x.h>
32 #include <plat/orion_nand.h>
33 #include <plat/ehci-orion.h>
34 #include <plat/time.h>
35 #include <plat/common.h>
36 #include <plat/addr-map.h>
37 #include "common.h"
38
39 /*****************************************************************************
40 * I/O Address Mapping
41 ****************************************************************************/
42 static struct map_desc orion5x_io_desc[] __initdata = {
43 {
44 .virtual = ORION5X_REGS_VIRT_BASE,
45 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
46 .length = ORION5X_REGS_SIZE,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = ORION5X_PCIE_IO_VIRT_BASE,
50 .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
51 .length = ORION5X_PCIE_IO_SIZE,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = ORION5X_PCI_IO_VIRT_BASE,
55 .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
56 .length = ORION5X_PCI_IO_SIZE,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = ORION5X_PCIE_WA_VIRT_BASE,
60 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
61 .length = ORION5X_PCIE_WA_SIZE,
62 .type = MT_DEVICE,
63 },
64 };
65
orion5x_map_io(void)66 void __init orion5x_map_io(void)
67 {
68 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
69 }
70
71
72 /*****************************************************************************
73 * EHCI0
74 ****************************************************************************/
orion5x_ehci0_init(void)75 void __init orion5x_ehci0_init(void)
76 {
77 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
78 EHCI_PHY_ORION);
79 }
80
81
82 /*****************************************************************************
83 * EHCI1
84 ****************************************************************************/
orion5x_ehci1_init(void)85 void __init orion5x_ehci1_init(void)
86 {
87 orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
88 }
89
90
91 /*****************************************************************************
92 * GE00
93 ****************************************************************************/
orion5x_eth_init(struct mv643xx_eth_platform_data * eth_data)94 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
95 {
96 orion_ge00_init(eth_data,
97 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
98 IRQ_ORION5X_ETH_ERR, orion5x_tclk,
99 MV643XX_TX_CSUM_DEFAULT_LIMIT);
100 }
101
102
103 /*****************************************************************************
104 * Ethernet switch
105 ****************************************************************************/
orion5x_eth_switch_init(struct dsa_platform_data * d,int irq)106 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
107 {
108 orion_ge00_switch_init(d, irq);
109 }
110
111
112 /*****************************************************************************
113 * I2C
114 ****************************************************************************/
orion5x_i2c_init(void)115 void __init orion5x_i2c_init(void)
116 {
117 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
118
119 }
120
121
122 /*****************************************************************************
123 * SATA
124 ****************************************************************************/
orion5x_sata_init(struct mv_sata_platform_data * sata_data)125 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
126 {
127 orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
128 }
129
130
131 /*****************************************************************************
132 * SPI
133 ****************************************************************************/
orion5x_spi_init()134 void __init orion5x_spi_init()
135 {
136 orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
137 }
138
139
140 /*****************************************************************************
141 * UART0
142 ****************************************************************************/
orion5x_uart0_init(void)143 void __init orion5x_uart0_init(void)
144 {
145 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
146 IRQ_ORION5X_UART0, orion5x_tclk);
147 }
148
149 /*****************************************************************************
150 * UART1
151 ****************************************************************************/
orion5x_uart1_init(void)152 void __init orion5x_uart1_init(void)
153 {
154 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
155 IRQ_ORION5X_UART1, orion5x_tclk);
156 }
157
158 /*****************************************************************************
159 * XOR engine
160 ****************************************************************************/
orion5x_xor_init(void)161 void __init orion5x_xor_init(void)
162 {
163 orion_xor0_init(ORION5X_XOR_PHYS_BASE,
164 ORION5X_XOR_PHYS_BASE + 0x200,
165 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
166 }
167
168 /*****************************************************************************
169 * Cryptographic Engines and Security Accelerator (CESA)
170 ****************************************************************************/
orion5x_crypto_init(void)171 static void __init orion5x_crypto_init(void)
172 {
173 orion5x_setup_sram_win();
174 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
175 SZ_8K, IRQ_ORION5X_CESA);
176 }
177
178 /*****************************************************************************
179 * Watchdog
180 ****************************************************************************/
orion5x_wdt_init(void)181 void __init orion5x_wdt_init(void)
182 {
183 orion_wdt_init(orion5x_tclk);
184 }
185
186
187 /*****************************************************************************
188 * Time handling
189 ****************************************************************************/
orion5x_init_early(void)190 void __init orion5x_init_early(void)
191 {
192 orion_time_set_base(TIMER_VIRT_BASE);
193 }
194
195 int orion5x_tclk;
196
orion5x_find_tclk(void)197 int __init orion5x_find_tclk(void)
198 {
199 u32 dev, rev;
200
201 orion5x_pcie_id(&dev, &rev);
202 if (dev == MV88F6183_DEV_ID &&
203 (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
204 return 133333333;
205
206 return 166666667;
207 }
208
orion5x_timer_init(void)209 static void orion5x_timer_init(void)
210 {
211 orion5x_tclk = orion5x_find_tclk();
212
213 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
214 IRQ_ORION5X_BRIDGE, orion5x_tclk);
215 }
216
217 struct sys_timer orion5x_timer = {
218 .init = orion5x_timer_init,
219 };
220
221
222 /*****************************************************************************
223 * General
224 ****************************************************************************/
225 /*
226 * Identify device ID and rev from PCIe configuration header space '0'.
227 */
orion5x_id(u32 * dev,u32 * rev,char ** dev_name)228 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
229 {
230 orion5x_pcie_id(dev, rev);
231
232 if (*dev == MV88F5281_DEV_ID) {
233 if (*rev == MV88F5281_REV_D2) {
234 *dev_name = "MV88F5281-D2";
235 } else if (*rev == MV88F5281_REV_D1) {
236 *dev_name = "MV88F5281-D1";
237 } else if (*rev == MV88F5281_REV_D0) {
238 *dev_name = "MV88F5281-D0";
239 } else {
240 *dev_name = "MV88F5281-Rev-Unsupported";
241 }
242 } else if (*dev == MV88F5182_DEV_ID) {
243 if (*rev == MV88F5182_REV_A2) {
244 *dev_name = "MV88F5182-A2";
245 } else {
246 *dev_name = "MV88F5182-Rev-Unsupported";
247 }
248 } else if (*dev == MV88F5181_DEV_ID) {
249 if (*rev == MV88F5181_REV_B1) {
250 *dev_name = "MV88F5181-Rev-B1";
251 } else if (*rev == MV88F5181L_REV_A1) {
252 *dev_name = "MV88F5181L-Rev-A1";
253 } else {
254 *dev_name = "MV88F5181(L)-Rev-Unsupported";
255 }
256 } else if (*dev == MV88F6183_DEV_ID) {
257 if (*rev == MV88F6183_REV_B0) {
258 *dev_name = "MV88F6183-Rev-B0";
259 } else {
260 *dev_name = "MV88F6183-Rev-Unsupported";
261 }
262 } else {
263 *dev_name = "Device-Unknown";
264 }
265 }
266
orion5x_init(void)267 void __init orion5x_init(void)
268 {
269 char *dev_name;
270 u32 dev, rev;
271
272 orion5x_id(&dev, &rev, &dev_name);
273 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
274
275 /*
276 * Setup Orion address map
277 */
278 orion5x_setup_cpu_mbus_bridge();
279
280 /*
281 * Don't issue "Wait for Interrupt" instruction if we are
282 * running on D0 5281 silicon.
283 */
284 if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
285 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
286 disable_hlt();
287 }
288
289 /*
290 * The 5082/5181l/5182/6082/6082l/6183 have crypto
291 * while 5180n/5181/5281 don't have crypto.
292 */
293 if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
294 dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
295 orion5x_crypto_init();
296
297 /*
298 * Register watchdog driver
299 */
300 orion5x_wdt_init();
301 }
302
orion5x_restart(char mode,const char * cmd)303 void orion5x_restart(char mode, const char *cmd)
304 {
305 /*
306 * Enable and issue soft reset
307 */
308 orion5x_setbits(RSTOUTn_MASK, (1 << 2));
309 orion5x_setbits(CPU_SOFT_RESET, 1);
310 mdelay(200);
311 orion5x_clrbits(CPU_SOFT_RESET, 1);
312 }
313
314 /*
315 * Many orion-based systems have buggy bootloader implementations.
316 * This is a common fixup for bogus memory tags.
317 */
tag_fixup_mem32(struct tag * t,char ** from,struct meminfo * meminfo)318 void __init tag_fixup_mem32(struct tag *t, char **from,
319 struct meminfo *meminfo)
320 {
321 for (; t->hdr.size; t = tag_next(t))
322 if (t->hdr.tag == ATAG_MEM &&
323 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
324 t->u.mem.start & ~PAGE_MASK)) {
325 printk(KERN_WARNING
326 "Clearing invalid memory bank %dKB@0x%08x\n",
327 t->u.mem.size / 1024, t->u.mem.start);
328 t->hdr.tag = 0;
329 }
330 }
331