1 /*
2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
3 *
4 * OMAP3 CPU IDLE Routines
5 *
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
8 *
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
11 *
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
14 *
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
17 *
18 * Based on pm.c for omap2
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
23 */
24
25 #include <linux/sched.h>
26 #include <linux/cpuidle.h>
27 #include <linux/export.h>
28 #include <linux/cpu_pm.h>
29
30 #include <plat/prcm.h>
31 #include <plat/irqs.h>
32 #include "powerdomain.h"
33 #include "clockdomain.h"
34
35 #include "pm.h"
36 #include "control.h"
37 #include "common.h"
38
39 #ifdef CONFIG_CPU_IDLE
40
41 /*
42 * The latencies/thresholds for various C states have
43 * to be configured from the respective board files.
44 * These are some default values (which might not provide
45 * the best power savings) used on boards which do not
46 * pass these details from the board file.
47 */
48 static struct cpuidle_params cpuidle_params_table[] = {
49 /* C1 */
50 {2 + 2, 5, 1},
51 /* C2 */
52 {10 + 10, 30, 1},
53 /* C3 */
54 {50 + 50, 300, 1},
55 /* C4 */
56 {1500 + 1800, 4000, 1},
57 /* C5 */
58 {2500 + 7500, 12000, 1},
59 /* C6 */
60 {3000 + 8500, 15000, 1},
61 /* C7 */
62 {10000 + 30000, 300000, 1},
63 };
64 #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
65
66 /* Mach specific information to be recorded in the C-state driver_data */
67 struct omap3_idle_statedata {
68 u32 mpu_state;
69 u32 core_state;
70 u8 valid;
71 };
72 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
73
74 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
75
_cpuidle_allow_idle(struct powerdomain * pwrdm,struct clockdomain * clkdm)76 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
77 struct clockdomain *clkdm)
78 {
79 clkdm_allow_idle(clkdm);
80 return 0;
81 }
82
_cpuidle_deny_idle(struct powerdomain * pwrdm,struct clockdomain * clkdm)83 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
84 struct clockdomain *clkdm)
85 {
86 clkdm_deny_idle(clkdm);
87 return 0;
88 }
89
__omap3_enter_idle(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)90 static int __omap3_enter_idle(struct cpuidle_device *dev,
91 struct cpuidle_driver *drv,
92 int index)
93 {
94 struct omap3_idle_statedata *cx =
95 cpuidle_get_statedata(&dev->states_usage[index]);
96 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
97
98 local_fiq_disable();
99
100 pwrdm_set_next_pwrst(mpu_pd, mpu_state);
101 pwrdm_set_next_pwrst(core_pd, core_state);
102
103 if (omap_irq_pending() || need_resched())
104 goto return_sleep_time;
105
106 /* Deny idle for C1 */
107 if (index == 0) {
108 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
109 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
110 }
111
112 /*
113 * Call idle CPU PM enter notifier chain so that
114 * VFP context is saved.
115 */
116 if (mpu_state == PWRDM_POWER_OFF)
117 cpu_pm_enter();
118
119 /* Execute ARM wfi */
120 omap_sram_idle();
121
122 /*
123 * Call idle CPU PM enter notifier chain to restore
124 * VFP context.
125 */
126 if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
127 cpu_pm_exit();
128
129 /* Re-allow idle for C1 */
130 if (index == 0) {
131 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
132 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
133 }
134
135 return_sleep_time:
136
137 local_fiq_enable();
138
139 return index;
140 }
141
142 /**
143 * omap3_enter_idle - Programs OMAP3 to enter the specified state
144 * @dev: cpuidle device
145 * @drv: cpuidle driver
146 * @index: the index of state to be entered
147 *
148 * Called from the CPUidle framework to program the device to the
149 * specified target state selected by the governor.
150 */
omap3_enter_idle(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)151 static inline int omap3_enter_idle(struct cpuidle_device *dev,
152 struct cpuidle_driver *drv,
153 int index)
154 {
155 return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
156 }
157
158 /**
159 * next_valid_state - Find next valid C-state
160 * @dev: cpuidle device
161 * @drv: cpuidle driver
162 * @index: Index of currently selected c-state
163 *
164 * If the state corresponding to index is valid, index is returned back
165 * to the caller. Else, this function searches for a lower c-state which is
166 * still valid (as defined in omap3_power_states[]) and returns its index.
167 *
168 * A state is valid if the 'valid' field is enabled and
169 * if it satisfies the enable_off_mode condition.
170 */
next_valid_state(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)171 static int next_valid_state(struct cpuidle_device *dev,
172 struct cpuidle_driver *drv,
173 int index)
174 {
175 struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
176 struct cpuidle_state *curr = &drv->states[index];
177 struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
178 u32 mpu_deepest_state = PWRDM_POWER_RET;
179 u32 core_deepest_state = PWRDM_POWER_RET;
180 int next_index = -1;
181
182 if (enable_off_mode) {
183 mpu_deepest_state = PWRDM_POWER_OFF;
184 /*
185 * Erratum i583: valable for ES rev < Es1.2 on 3630.
186 * CORE OFF mode is not supported in a stable form, restrict
187 * instead the CORE state to RET.
188 */
189 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
190 core_deepest_state = PWRDM_POWER_OFF;
191 }
192
193 /* Check if current state is valid */
194 if ((cx->valid) &&
195 (cx->mpu_state >= mpu_deepest_state) &&
196 (cx->core_state >= core_deepest_state)) {
197 return index;
198 } else {
199 int idx = OMAP3_NUM_STATES - 1;
200
201 /* Reach the current state starting at highest C-state */
202 for (; idx >= 0; idx--) {
203 if (&drv->states[idx] == curr) {
204 next_index = idx;
205 break;
206 }
207 }
208
209 /* Should never hit this condition */
210 WARN_ON(next_index == -1);
211
212 /*
213 * Drop to next valid state.
214 * Start search from the next (lower) state.
215 */
216 idx--;
217 for (; idx >= 0; idx--) {
218 cx = cpuidle_get_statedata(&dev->states_usage[idx]);
219 if ((cx->valid) &&
220 (cx->mpu_state >= mpu_deepest_state) &&
221 (cx->core_state >= core_deepest_state)) {
222 next_index = idx;
223 break;
224 }
225 }
226 /*
227 * C1 is always valid.
228 * So, no need to check for 'next_index == -1' outside
229 * this loop.
230 */
231 }
232
233 return next_index;
234 }
235
236 /**
237 * omap3_enter_idle_bm - Checks for any bus activity
238 * @dev: cpuidle device
239 * @drv: cpuidle driver
240 * @index: array index of target state to be programmed
241 *
242 * This function checks for any pending activity and then programs
243 * the device to the specified or a safer state.
244 */
omap3_enter_idle_bm(struct cpuidle_device * dev,struct cpuidle_driver * drv,int index)245 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
246 struct cpuidle_driver *drv,
247 int index)
248 {
249 int new_state_idx;
250 u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
251 struct omap3_idle_statedata *cx;
252 int ret;
253
254 /*
255 * Prevent idle completely if CAM is active.
256 * CAM does not have wakeup capability in OMAP3.
257 */
258 cam_state = pwrdm_read_pwrst(cam_pd);
259 if (cam_state == PWRDM_POWER_ON) {
260 new_state_idx = drv->safe_state_index;
261 goto select_state;
262 }
263
264 /*
265 * FIXME: we currently manage device-specific idle states
266 * for PER and CORE in combination with CPU-specific
267 * idle states. This is wrong, and device-specific
268 * idle management needs to be separated out into
269 * its own code.
270 */
271
272 /*
273 * Prevent PER off if CORE is not in retention or off as this
274 * would disable PER wakeups completely.
275 */
276 cx = cpuidle_get_statedata(&dev->states_usage[index]);
277 core_next_state = cx->core_state;
278 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
279 if ((per_next_state == PWRDM_POWER_OFF) &&
280 (core_next_state > PWRDM_POWER_RET))
281 per_next_state = PWRDM_POWER_RET;
282
283 /* Are we changing PER target state? */
284 if (per_next_state != per_saved_state)
285 pwrdm_set_next_pwrst(per_pd, per_next_state);
286
287 new_state_idx = next_valid_state(dev, drv, index);
288
289 select_state:
290 ret = omap3_enter_idle(dev, drv, new_state_idx);
291
292 /* Restore original PER state if it was modified */
293 if (per_next_state != per_saved_state)
294 pwrdm_set_next_pwrst(per_pd, per_saved_state);
295
296 return ret;
297 }
298
299 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
300
omap3_pm_init_cpuidle(struct cpuidle_params * cpuidle_board_params)301 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
302 {
303 int i;
304
305 if (!cpuidle_board_params)
306 return;
307
308 for (i = 0; i < OMAP3_NUM_STATES; i++) {
309 cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
310 cpuidle_params_table[i].exit_latency =
311 cpuidle_board_params[i].exit_latency;
312 cpuidle_params_table[i].target_residency =
313 cpuidle_board_params[i].target_residency;
314 }
315 return;
316 }
317
318 struct cpuidle_driver omap3_idle_driver = {
319 .name = "omap3_idle",
320 .owner = THIS_MODULE,
321 };
322
323 /* Helper to fill the C-state common data*/
_fill_cstate(struct cpuidle_driver * drv,int idx,const char * descr)324 static inline void _fill_cstate(struct cpuidle_driver *drv,
325 int idx, const char *descr)
326 {
327 struct cpuidle_state *state = &drv->states[idx];
328
329 state->exit_latency = cpuidle_params_table[idx].exit_latency;
330 state->target_residency = cpuidle_params_table[idx].target_residency;
331 state->flags = CPUIDLE_FLAG_TIME_VALID;
332 state->enter = omap3_enter_idle_bm;
333 sprintf(state->name, "C%d", idx + 1);
334 strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
335
336 }
337
338 /* Helper to register the driver_data */
_fill_cstate_usage(struct cpuidle_device * dev,int idx)339 static inline struct omap3_idle_statedata *_fill_cstate_usage(
340 struct cpuidle_device *dev,
341 int idx)
342 {
343 struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
344 struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
345
346 cx->valid = cpuidle_params_table[idx].valid;
347 cpuidle_set_statedata(state_usage, cx);
348
349 return cx;
350 }
351
352 /**
353 * omap3_idle_init - Init routine for OMAP3 idle
354 *
355 * Registers the OMAP3 specific cpuidle driver to the cpuidle
356 * framework with the valid set of states.
357 */
omap3_idle_init(void)358 int __init omap3_idle_init(void)
359 {
360 struct cpuidle_device *dev;
361 struct cpuidle_driver *drv = &omap3_idle_driver;
362 struct omap3_idle_statedata *cx;
363
364 mpu_pd = pwrdm_lookup("mpu_pwrdm");
365 core_pd = pwrdm_lookup("core_pwrdm");
366 per_pd = pwrdm_lookup("per_pwrdm");
367 cam_pd = pwrdm_lookup("cam_pwrdm");
368
369
370 drv->safe_state_index = -1;
371 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
372
373 /* C1 . MPU WFI + Core active */
374 _fill_cstate(drv, 0, "MPU ON + CORE ON");
375 (&drv->states[0])->enter = omap3_enter_idle;
376 drv->safe_state_index = 0;
377 cx = _fill_cstate_usage(dev, 0);
378 cx->valid = 1; /* C1 is always valid */
379 cx->mpu_state = PWRDM_POWER_ON;
380 cx->core_state = PWRDM_POWER_ON;
381
382 /* C2 . MPU WFI + Core inactive */
383 _fill_cstate(drv, 1, "MPU ON + CORE ON");
384 cx = _fill_cstate_usage(dev, 1);
385 cx->mpu_state = PWRDM_POWER_ON;
386 cx->core_state = PWRDM_POWER_ON;
387
388 /* C3 . MPU CSWR + Core inactive */
389 _fill_cstate(drv, 2, "MPU RET + CORE ON");
390 cx = _fill_cstate_usage(dev, 2);
391 cx->mpu_state = PWRDM_POWER_RET;
392 cx->core_state = PWRDM_POWER_ON;
393
394 /* C4 . MPU OFF + Core inactive */
395 _fill_cstate(drv, 3, "MPU OFF + CORE ON");
396 cx = _fill_cstate_usage(dev, 3);
397 cx->mpu_state = PWRDM_POWER_OFF;
398 cx->core_state = PWRDM_POWER_ON;
399
400 /* C5 . MPU RET + Core RET */
401 _fill_cstate(drv, 4, "MPU RET + CORE RET");
402 cx = _fill_cstate_usage(dev, 4);
403 cx->mpu_state = PWRDM_POWER_RET;
404 cx->core_state = PWRDM_POWER_RET;
405
406 /* C6 . MPU OFF + Core RET */
407 _fill_cstate(drv, 5, "MPU OFF + CORE RET");
408 cx = _fill_cstate_usage(dev, 5);
409 cx->mpu_state = PWRDM_POWER_OFF;
410 cx->core_state = PWRDM_POWER_RET;
411
412 /* C7 . MPU OFF + Core OFF */
413 _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
414 cx = _fill_cstate_usage(dev, 6);
415 /*
416 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
417 * enable OFF mode in a stable form for previous revisions.
418 * We disable C7 state as a result.
419 */
420 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
421 cx->valid = 0;
422 pr_warn("%s: core off state C7 disabled due to i583\n",
423 __func__);
424 }
425 cx->mpu_state = PWRDM_POWER_OFF;
426 cx->core_state = PWRDM_POWER_OFF;
427
428 drv->state_count = OMAP3_NUM_STATES;
429 cpuidle_register_driver(&omap3_idle_driver);
430
431 dev->state_count = OMAP3_NUM_STATES;
432 if (cpuidle_register_device(dev)) {
433 printk(KERN_ERR "%s: CPUidle register device failed\n",
434 __func__);
435 return -EIO;
436 }
437
438 return 0;
439 }
440 #else
omap3_idle_init(void)441 int __init omap3_idle_init(void)
442 {
443 return 0;
444 }
445 #endif /* CONFIG_CPU_IDLE */
446