1 /*
2 * arch/arm/mach-kirkwood/addr-map.c
3 *
4 * Address map functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/mbus.h>
14 #include <linux/io.h>
15 #include <mach/hardware.h>
16 #include <plat/addr-map.h>
17 #include "common.h"
18
19 /*
20 * Generic Address Decode Windows bit settings
21 */
22 #define TARGET_DEV_BUS 1
23 #define TARGET_SRAM 3
24 #define TARGET_PCIE 4
25 #define ATTR_DEV_SPI_ROM 0x1e
26 #define ATTR_DEV_BOOT 0x1d
27 #define ATTR_DEV_NAND 0x2f
28 #define ATTR_DEV_CS3 0x37
29 #define ATTR_DEV_CS2 0x3b
30 #define ATTR_DEV_CS1 0x3d
31 #define ATTR_DEV_CS0 0x3e
32 #define ATTR_PCIE_IO 0xe0
33 #define ATTR_PCIE_MEM 0xe8
34 #define ATTR_PCIE1_IO 0xd0
35 #define ATTR_PCIE1_MEM 0xd8
36 #define ATTR_SRAM 0x01
37
38 /*
39 * Description of the windows needed by the platform code
40 */
41 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
42 .num_wins = 8,
43 .remappable_wins = 4,
44 .bridge_virt_base = BRIDGE_VIRT_BASE,
45 };
46
47 static const struct __initdata orion_addr_map_info addr_map_info[] = {
48 /*
49 * Windows for PCIe IO+MEM space.
50 */
51 { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
52 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
53 },
54 { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
55 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
56 },
57 { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
58 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
59 },
60 { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
61 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
62 },
63 /*
64 * Window for NAND controller.
65 */
66 { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
67 TARGET_DEV_BUS, ATTR_DEV_NAND, -1
68 },
69 /*
70 * Window for SRAM.
71 */
72 { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
73 TARGET_SRAM, ATTR_SRAM, -1
74 },
75 /* End marker */
76 { -1, 0, 0, 0, 0, 0 }
77 };
78
kirkwood_setup_cpu_mbus(void)79 void __init kirkwood_setup_cpu_mbus(void)
80 {
81 /*
82 * Disable, clear and configure windows.
83 */
84 orion_config_wins(&addr_map_cfg, addr_map_info);
85
86 /*
87 * Setup MBUS dram target info.
88 */
89 orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
90 }
91