1 /* linux/arch/arm/mach-exynos4/mach-armlex4210.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/gpio.h>
12 #include <linux/io.h>
13 #include <linux/mmc/host.h>
14 #include <linux/platform_device.h>
15 #include <linux/serial_core.h>
16 #include <linux/smsc911x.h>
17
18 #include <asm/mach/arch.h>
19 #include <asm/hardware/gic.h>
20 #include <asm/mach-types.h>
21
22 #include <plat/cpu.h>
23 #include <plat/devs.h>
24 #include <plat/gpio-cfg.h>
25 #include <plat/regs-serial.h>
26 #include <plat/regs-srom.h>
27 #include <plat/sdhci.h>
28
29 #include <mach/map.h>
30
31 #include "common.h"
32
33 /* Following are default values for UCON, ULCON and UFCON UART registers */
34 #define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
35 S3C2410_UCON_RXILEVEL | \
36 S3C2410_UCON_TXIRQMODE | \
37 S3C2410_UCON_RXIRQMODE | \
38 S3C2410_UCON_RXFIFO_TOI | \
39 S3C2443_UCON_RXERR_IRQEN)
40
41 #define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
42
43 #define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
44 S5PV210_UFCON_TXTRIG4 | \
45 S5PV210_UFCON_RXTRIG4)
46
47 static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
48 [0] = {
49 .hwport = 0,
50 .flags = 0,
51 .ucon = ARMLEX4210_UCON_DEFAULT,
52 .ulcon = ARMLEX4210_ULCON_DEFAULT,
53 .ufcon = ARMLEX4210_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .flags = 0,
58 .ucon = ARMLEX4210_UCON_DEFAULT,
59 .ulcon = ARMLEX4210_ULCON_DEFAULT,
60 .ufcon = ARMLEX4210_UFCON_DEFAULT,
61 },
62 [2] = {
63 .hwport = 2,
64 .flags = 0,
65 .ucon = ARMLEX4210_UCON_DEFAULT,
66 .ulcon = ARMLEX4210_ULCON_DEFAULT,
67 .ufcon = ARMLEX4210_UFCON_DEFAULT,
68 },
69 [3] = {
70 .hwport = 3,
71 .flags = 0,
72 .ucon = ARMLEX4210_UCON_DEFAULT,
73 .ulcon = ARMLEX4210_ULCON_DEFAULT,
74 .ufcon = ARMLEX4210_UFCON_DEFAULT,
75 },
76 };
77
78 static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_PERMANENT,
80 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
81 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
82 .max_width = 8,
83 .host_caps = MMC_CAP_8_BIT_DATA,
84 #endif
85 };
86
87 static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
88 .cd_type = S3C_SDHCI_CD_GPIO,
89 .ext_cd_gpio = EXYNOS4_GPX2(5),
90 .ext_cd_gpio_invert = 1,
91 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
92 .max_width = 4,
93 };
94
95 static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
96 .cd_type = S3C_SDHCI_CD_PERMANENT,
97 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
98 .max_width = 4,
99 };
100
armlex4210_sdhci_init(void)101 static void __init armlex4210_sdhci_init(void)
102 {
103 s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
104 s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
105 s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
106 }
107
armlex4210_wlan_init(void)108 static void __init armlex4210_wlan_init(void)
109 {
110 /* enable */
111 s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
112 s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
113
114 /* reset */
115 s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
116 s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
117
118 /* wakeup */
119 s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
120 s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
121 }
122
123 static struct resource armlex4210_smsc911x_resources[] = {
124 [0] = {
125 .start = EXYNOS4_PA_SROM_BANK(3),
126 .end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
127 .flags = IORESOURCE_MEM,
128 },
129 [1] = {
130 .start = IRQ_EINT(27),
131 .end = IRQ_EINT(27),
132 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
133 },
134 };
135
136 static struct smsc911x_platform_config smsc9215_config = {
137 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
138 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
139 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
140 .phy_interface = PHY_INTERFACE_MODE_MII,
141 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
142 };
143
144 static struct platform_device armlex4210_smsc911x = {
145 .name = "smsc911x",
146 .id = -1,
147 .num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
148 .resource = armlex4210_smsc911x_resources,
149 .dev = {
150 .platform_data = &smsc9215_config,
151 },
152 };
153
154 static struct platform_device *armlex4210_devices[] __initdata = {
155 &s3c_device_hsmmc0,
156 &s3c_device_hsmmc2,
157 &s3c_device_hsmmc3,
158 &s3c_device_rtc,
159 &s3c_device_wdt,
160 &exynos4_device_sysmmu,
161 &samsung_asoc_dma,
162 &armlex4210_smsc911x,
163 &exynos4_device_ahci,
164 };
165
armlex4210_smsc911x_init(void)166 static void __init armlex4210_smsc911x_init(void)
167 {
168 u32 cs1;
169
170 /* configure nCS1 width to 16 bits */
171 cs1 = __raw_readl(S5P_SROM_BW) &
172 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
173 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
174 (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
175 (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
176 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
177 S5P_SROM_BW__NCS1__SHIFT;
178 __raw_writel(cs1, S5P_SROM_BW);
179
180 /* set timing for nCS1 suitable for ethernet chip */
181 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
182 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
183 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
184 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
185 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
186 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
187 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
188 }
189
armlex4210_map_io(void)190 static void __init armlex4210_map_io(void)
191 {
192 exynos_init_io(NULL, 0);
193 s3c24xx_init_clocks(24000000);
194 s3c24xx_init_uarts(armlex4210_uartcfgs,
195 ARRAY_SIZE(armlex4210_uartcfgs));
196 }
197
armlex4210_machine_init(void)198 static void __init armlex4210_machine_init(void)
199 {
200 armlex4210_smsc911x_init();
201
202 armlex4210_sdhci_init();
203
204 armlex4210_wlan_init();
205
206 platform_add_devices(armlex4210_devices,
207 ARRAY_SIZE(armlex4210_devices));
208 }
209
210 MACHINE_START(ARMLEX4210, "ARMLEX4210")
211 /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
212 .atag_offset = 0x100,
213 .init_irq = exynos4_init_irq,
214 .map_io = armlex4210_map_io,
215 .handle_irq = gic_handle_irq,
216 .init_machine = armlex4210_machine_init,
217 .timer = &exynos4_timer,
218 .restart = exynos4_restart,
219 MACHINE_END
220