1 /*
2 * Copyright 1999 - 2003 ARM Limited
3 * Copyright 2000 Deep Blue Solutions Ltd
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/clockchips.h>
14 #include <linux/io.h>
15 #include <asm/mach/map.h>
16 #include <asm/mach/time.h>
17 #include <asm/mach/irq.h>
18 #include <asm/hardware/gic.h>
19 #include <asm/hardware/cache-l2x0.h>
20 #include <mach/cns3xxx.h>
21 #include "core.h"
22
23 static struct map_desc cns3xxx_io_desc[] __initdata = {
24 {
25 .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
26 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
27 .length = SZ_8K,
28 .type = MT_DEVICE,
29 }, {
30 .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
31 .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
32 .length = SZ_4K,
33 .type = MT_DEVICE,
34 }, {
35 .virtual = CNS3XXX_GPIOA_BASE_VIRT,
36 .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
37 .length = SZ_4K,
38 .type = MT_DEVICE,
39 }, {
40 .virtual = CNS3XXX_GPIOB_BASE_VIRT,
41 .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
42 .length = SZ_4K,
43 .type = MT_DEVICE,
44 }, {
45 .virtual = CNS3XXX_MISC_BASE_VIRT,
46 .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
47 .length = SZ_4K,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = CNS3XXX_PM_BASE_VIRT,
51 .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
52 .length = SZ_4K,
53 .type = MT_DEVICE,
54 },
55 };
56
cns3xxx_map_io(void)57 void __init cns3xxx_map_io(void)
58 {
59 iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
60 }
61
62 /* used by entry-macro.S */
cns3xxx_init_irq(void)63 void __init cns3xxx_init_irq(void)
64 {
65 gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
66 IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
67 }
68
cns3xxx_power_off(void)69 void cns3xxx_power_off(void)
70 {
71 u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
72 u32 clkctrl;
73
74 printk(KERN_INFO "powering system down...\n");
75
76 clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
77 clkctrl &= 0xfffff1ff;
78 clkctrl |= (0x5 << 9); /* Hibernate */
79 writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
80
81 }
82
83 /*
84 * Timer
85 */
86 static void __iomem *cns3xxx_tmr1;
87
cns3xxx_timer_set_mode(enum clock_event_mode mode,struct clock_event_device * clk)88 static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
89 struct clock_event_device *clk)
90 {
91 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
92 int pclk = cns3xxx_cpu_clock() / 8;
93 int reload;
94
95 switch (mode) {
96 case CLOCK_EVT_MODE_PERIODIC:
97 reload = pclk * 20 / (3 * HZ) * 0x25000;
98 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
99 ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
100 break;
101 case CLOCK_EVT_MODE_ONESHOT:
102 /* period set, and timer enabled in 'next_event' hook */
103 ctrl |= (1 << 2) | (1 << 9);
104 break;
105 case CLOCK_EVT_MODE_UNUSED:
106 case CLOCK_EVT_MODE_SHUTDOWN:
107 default:
108 ctrl = 0;
109 }
110
111 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
112 }
113
cns3xxx_timer_set_next_event(unsigned long evt,struct clock_event_device * unused)114 static int cns3xxx_timer_set_next_event(unsigned long evt,
115 struct clock_event_device *unused)
116 {
117 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
118
119 writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
120 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
121
122 return 0;
123 }
124
125 static struct clock_event_device cns3xxx_tmr1_clockevent = {
126 .name = "cns3xxx timer1",
127 .shift = 8,
128 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
129 .set_mode = cns3xxx_timer_set_mode,
130 .set_next_event = cns3xxx_timer_set_next_event,
131 .rating = 350,
132 .cpumask = cpu_all_mask,
133 };
134
cns3xxx_clockevents_init(unsigned int timer_irq)135 static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
136 {
137 cns3xxx_tmr1_clockevent.irq = timer_irq;
138 cns3xxx_tmr1_clockevent.mult =
139 div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC,
140 cns3xxx_tmr1_clockevent.shift);
141 cns3xxx_tmr1_clockevent.max_delta_ns =
142 clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
143 cns3xxx_tmr1_clockevent.min_delta_ns =
144 clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
145
146 clockevents_register_device(&cns3xxx_tmr1_clockevent);
147 }
148
149 /*
150 * IRQ handler for the timer
151 */
cns3xxx_timer_interrupt(int irq,void * dev_id)152 static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
153 {
154 struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
155 u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
156 u32 val;
157
158 /* Clear the interrupt */
159 val = readl(stat);
160 writel(val & ~(1 << 2), stat);
161
162 evt->event_handler(evt);
163
164 return IRQ_HANDLED;
165 }
166
167 static struct irqaction cns3xxx_timer_irq = {
168 .name = "timer",
169 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
170 .handler = cns3xxx_timer_interrupt,
171 };
172
173 /*
174 * Set up the clock source and clock events devices
175 */
__cns3xxx_timer_init(unsigned int timer_irq)176 static void __init __cns3xxx_timer_init(unsigned int timer_irq)
177 {
178 u32 val;
179 u32 irq_mask;
180
181 /*
182 * Initialise to a known state (all timers off)
183 */
184
185 /* disable timer1 and timer2 */
186 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
187 /* stop free running timer3 */
188 writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
189
190 /* timer1 */
191 writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
192 writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
193
194 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
195 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
196
197 /* mask irq, non-mask timer1 overflow */
198 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
199 irq_mask &= ~(1 << 2);
200 irq_mask |= 0x03;
201 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
202
203 /* down counter */
204 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
205 val |= (1 << 9);
206 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
207
208 /* timer2 */
209 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
210 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
211
212 /* mask irq */
213 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
214 irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
215 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
216
217 /* down counter */
218 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
219 val |= (1 << 10);
220 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
221
222 /* Make irqs happen for the system timer */
223 setup_irq(timer_irq, &cns3xxx_timer_irq);
224
225 cns3xxx_clockevents_init(timer_irq);
226 }
227
cns3xxx_timer_init(void)228 static void __init cns3xxx_timer_init(void)
229 {
230 cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);
231
232 __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
233 }
234
235 struct sys_timer cns3xxx_timer = {
236 .init = cns3xxx_timer_init,
237 };
238
239 #ifdef CONFIG_CACHE_L2X0
240
cns3xxx_l2x0_init(void)241 void __init cns3xxx_l2x0_init(void)
242 {
243 void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
244 u32 val;
245
246 if (WARN_ON(!base))
247 return;
248
249 /*
250 * Tag RAM Control register
251 *
252 * bit[10:8] - 1 cycle of write accesses latency
253 * bit[6:4] - 1 cycle of read accesses latency
254 * bit[3:0] - 1 cycle of setup latency
255 *
256 * 1 cycle of latency for setup, read and write accesses
257 */
258 val = readl(base + L2X0_TAG_LATENCY_CTRL);
259 val &= 0xfffff888;
260 writel(val, base + L2X0_TAG_LATENCY_CTRL);
261
262 /*
263 * Data RAM Control register
264 *
265 * bit[10:8] - 1 cycles of write accesses latency
266 * bit[6:4] - 1 cycles of read accesses latency
267 * bit[3:0] - 1 cycle of setup latency
268 *
269 * 1 cycle of latency for setup, read and write accesses
270 */
271 val = readl(base + L2X0_DATA_LATENCY_CTRL);
272 val &= 0xfffff888;
273 writel(val, base + L2X0_DATA_LATENCY_CTRL);
274
275 /* 32 KiB, 8-way, parity disable */
276 l2x0_init(base, 0x00540000, 0xfe000fff);
277 }
278
279 #endif /* CONFIG_CACHE_L2X0 */
280