1 /*
2 * Cavium Networks CNS3420 Validation Board
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 *
11 * This file is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License, Version 2, as
13 * published by the Free Software Foundation.
14 */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/compiler.h>
19 #include <linux/io.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_8250.h>
23 #include <linux/platform_device.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/physmap.h>
26 #include <linux/mtd/partitions.h>
27 #include <asm/setup.h>
28 #include <asm/mach-types.h>
29 #include <asm/hardware/gic.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/time.h>
33 #include <mach/cns3xxx.h>
34 #include <mach/irqs.h>
35 #include "core.h"
36 #include "devices.h"
37
38 /*
39 * NOR Flash
40 */
41 static struct mtd_partition cns3420_nor_partitions[] = {
42 {
43 .name = "uboot",
44 .size = 0x00040000,
45 .offset = 0,
46 .mask_flags = MTD_WRITEABLE,
47 }, {
48 .name = "kernel",
49 .size = 0x004C0000,
50 .offset = MTDPART_OFS_APPEND,
51 }, {
52 .name = "filesystem",
53 .size = 0x7000000,
54 .offset = MTDPART_OFS_APPEND,
55 }, {
56 .name = "filesystem2",
57 .size = 0x0AE0000,
58 .offset = MTDPART_OFS_APPEND,
59 }, {
60 .name = "ubootenv",
61 .size = MTDPART_SIZ_FULL,
62 .offset = MTDPART_OFS_APPEND,
63 },
64 };
65
66 static struct physmap_flash_data cns3420_nor_pdata = {
67 .width = 2,
68 .parts = cns3420_nor_partitions,
69 .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
70 };
71
72 static struct resource cns3420_nor_res = {
73 .start = CNS3XXX_FLASH_BASE,
74 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
75 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
76 };
77
78 static struct platform_device cns3420_nor_pdev = {
79 .name = "physmap-flash",
80 .id = 0,
81 .resource = &cns3420_nor_res,
82 .num_resources = 1,
83 .dev = {
84 .platform_data = &cns3420_nor_pdata,
85 },
86 };
87
88 /*
89 * UART
90 */
cns3420_early_serial_setup(void)91 static void __init cns3420_early_serial_setup(void)
92 {
93 #ifdef CONFIG_SERIAL_8250_CONSOLE
94 static struct uart_port cns3420_serial_port = {
95 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
96 .mapbase = CNS3XXX_UART0_BASE,
97 .irq = IRQ_CNS3XXX_UART0,
98 .iotype = UPIO_MEM,
99 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
100 .regshift = 2,
101 .uartclk = 24000000,
102 .line = 0,
103 .type = PORT_16550A,
104 .fifosize = 16,
105 };
106
107 early_serial_setup(&cns3420_serial_port);
108 #endif
109 }
110
111 /*
112 * USB
113 */
114 static struct resource cns3xxx_usb_ehci_resources[] = {
115 [0] = {
116 .start = CNS3XXX_USB_BASE,
117 .end = CNS3XXX_USB_BASE + SZ_16M - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = IRQ_CNS3XXX_USB_EHCI,
122 .flags = IORESOURCE_IRQ,
123 },
124 };
125
126 static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
127
128 static struct platform_device cns3xxx_usb_ehci_device = {
129 .name = "cns3xxx-ehci",
130 .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
131 .resource = cns3xxx_usb_ehci_resources,
132 .dev = {
133 .dma_mask = &cns3xxx_usb_ehci_dma_mask,
134 .coherent_dma_mask = DMA_BIT_MASK(32),
135 },
136 };
137
138 static struct resource cns3xxx_usb_ohci_resources[] = {
139 [0] = {
140 .start = CNS3XXX_USB_OHCI_BASE,
141 .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
142 .flags = IORESOURCE_MEM,
143 },
144 [1] = {
145 .start = IRQ_CNS3XXX_USB_OHCI,
146 .flags = IORESOURCE_IRQ,
147 },
148 };
149
150 static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
151
152 static struct platform_device cns3xxx_usb_ohci_device = {
153 .name = "cns3xxx-ohci",
154 .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
155 .resource = cns3xxx_usb_ohci_resources,
156 .dev = {
157 .dma_mask = &cns3xxx_usb_ohci_dma_mask,
158 .coherent_dma_mask = DMA_BIT_MASK(32),
159 },
160 };
161
162 /*
163 * Initialization
164 */
165 static struct platform_device *cns3420_pdevs[] __initdata = {
166 &cns3420_nor_pdev,
167 &cns3xxx_usb_ehci_device,
168 &cns3xxx_usb_ohci_device,
169 };
170
cns3420_init(void)171 static void __init cns3420_init(void)
172 {
173 cns3xxx_l2x0_init();
174
175 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
176
177 cns3xxx_ahci_init();
178 cns3xxx_sdhci_init();
179
180 pm_power_off = cns3xxx_power_off;
181 }
182
183 static struct map_desc cns3420_io_desc[] __initdata = {
184 {
185 .virtual = CNS3XXX_UART0_BASE_VIRT,
186 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
187 .length = SZ_4K,
188 .type = MT_DEVICE,
189 },
190 };
191
cns3420_map_io(void)192 static void __init cns3420_map_io(void)
193 {
194 cns3xxx_map_io();
195 iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
196
197 cns3420_early_serial_setup();
198 }
199
200 MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
201 .atag_offset = 0x100,
202 .map_io = cns3420_map_io,
203 .init_irq = cns3xxx_init_irq,
204 .timer = &cns3xxx_timer,
205 .handle_irq = gic_handle_irq,
206 .init_machine = cns3420_init,
207 .restart = cns3xxx_restart,
208 MACHINE_END
209