1 /* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 #ifndef MDP_H 14 #define MDP_H 15 16 #include <linux/kernel.h> 17 #include <linux/sched.h> 18 #include <linux/time.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/fb.h> 22 #include <linux/hrtimer.h> 23 #include "msm_mdp.h" 24 25 #include <mach/hardware.h> 26 #include <linux/io.h> 27 28 #include <asm/system.h> 29 #include <asm/mach-types.h> 30 31 #include "msm_fb_panel.h" 32 33 #ifdef CONFIG_MDP_PPP_ASYNC_OP 34 #include "mdp_ppp_dq.h" 35 #endif 36 37 #ifdef BIT 38 #undef BIT 39 #endif 40 41 #define BIT(x) (1<<(x)) 42 43 #define MDPOP_NOP 0 44 #define MDPOP_LR BIT(0) /* left to right flip */ 45 #define MDPOP_UD BIT(1) /* up and down flip */ 46 #define MDPOP_ROT90 BIT(2) /* rotate image to 90 degree */ 47 #define MDPOP_ROT180 (MDPOP_UD|MDPOP_LR) 48 #define MDPOP_ROT270 (MDPOP_ROT90|MDPOP_UD|MDPOP_LR) 49 #define MDPOP_ASCALE BIT(7) 50 #define MDPOP_ALPHAB BIT(8) /* enable alpha blending */ 51 #define MDPOP_TRANSP BIT(9) /* enable transparency */ 52 #define MDPOP_DITHER BIT(10) /* enable dither */ 53 #define MDPOP_SHARPENING BIT(11) /* enable sharpening */ 54 #define MDPOP_BLUR BIT(12) /* enable blur */ 55 #define MDPOP_FG_PM_ALPHA BIT(13) 56 57 struct mdp_table_entry { 58 uint32_t reg; 59 uint32_t val; 60 }; 61 62 extern struct mdp_ccs mdp_ccs_yuv2rgb ; 63 extern struct mdp_ccs mdp_ccs_rgb2yuv ; 64 65 /* 66 * MDP Image Structure 67 */ 68 typedef struct mdpImg_ { 69 uint32 imgType; /* Image type */ 70 uint32 *bmy_addr; /* bitmap or y addr */ 71 uint32 *cbcr_addr; /* cbcr addr */ 72 uint32 width; /* image width */ 73 uint32 mdpOp; /* image opertion (rotation,flip up/down, alpha/tp) */ 74 uint32 tpVal; /* transparency color */ 75 uint32 alpha; /* alpha percentage 0%(0x0) ~ 100%(0x100) */ 76 int sp_value; /* sharpening strength */ 77 } MDPIMG; 78 79 #ifdef CONFIG_MDP_PPP_ASYNC_OP 80 #define MDP_OUTP(addr, data) mdp_ppp_outdw((uint32_t)(addr), \ 81 (uint32_t)(data)) 82 #else 83 #define MDP_OUTP(addr, data) outpdw((addr), (data)) 84 #endif 85 86 #define MDP_KTIME2USEC(kt) (kt.tv.sec*1000000 + kt.tv.nsec/1000) 87 88 #define MDP_BASE msm_mdp_base 89 90 typedef enum { 91 MDP_BC_SCALE_POINT2_POINT4, 92 MDP_BC_SCALE_POINT4_POINT6, 93 MDP_BC_SCALE_POINT6_POINT8, 94 MDP_BC_SCALE_POINT8_1, 95 MDP_BC_SCALE_UP, 96 MDP_PR_SCALE_POINT2_POINT4, 97 MDP_PR_SCALE_POINT4_POINT6, 98 MDP_PR_SCALE_POINT6_POINT8, 99 MDP_PR_SCALE_POINT8_1, 100 MDP_PR_SCALE_UP, 101 MDP_SCALE_BLUR, 102 MDP_INIT_SCALE 103 } MDP_SCALE_MODE; 104 105 typedef enum { 106 MDP_BLOCK_POWER_OFF, 107 MDP_BLOCK_POWER_ON 108 } MDP_BLOCK_POWER_STATE; 109 110 typedef enum { 111 MDP_MASTER_BLOCK, 112 MDP_CMD_BLOCK, 113 MDP_PPP_BLOCK, 114 MDP_DMA2_BLOCK, 115 MDP_DMA3_BLOCK, 116 MDP_DMA_S_BLOCK, 117 MDP_DMA_E_BLOCK, 118 MDP_OVERLAY0_BLOCK, 119 MDP_OVERLAY1_BLOCK, 120 MDP_MAX_BLOCK 121 } MDP_BLOCK_TYPE; 122 123 /* Let's keep Q Factor power of 2 for optimization */ 124 #define MDP_SCALE_Q_FACTOR 512 125 126 #ifdef CONFIG_FB_MSM_MDP31 127 #define MDP_MAX_X_SCALE_FACTOR (MDP_SCALE_Q_FACTOR*8) 128 #define MDP_MIN_X_SCALE_FACTOR (MDP_SCALE_Q_FACTOR/8) 129 #define MDP_MAX_Y_SCALE_FACTOR (MDP_SCALE_Q_FACTOR*8) 130 #define MDP_MIN_Y_SCALE_FACTOR (MDP_SCALE_Q_FACTOR/8) 131 #else 132 #define MDP_MAX_X_SCALE_FACTOR (MDP_SCALE_Q_FACTOR*4) 133 #define MDP_MIN_X_SCALE_FACTOR (MDP_SCALE_Q_FACTOR/4) 134 #define MDP_MAX_Y_SCALE_FACTOR (MDP_SCALE_Q_FACTOR*4) 135 #define MDP_MIN_Y_SCALE_FACTOR (MDP_SCALE_Q_FACTOR/4) 136 #endif 137 138 /* SHIM Q Factor */ 139 #define PHI_Q_FACTOR 29 140 #define PQF_PLUS_5 (PHI_Q_FACTOR + 5) /* due to 32 phases */ 141 #define PQF_PLUS_4 (PHI_Q_FACTOR + 4) 142 #define PQF_PLUS_2 (PHI_Q_FACTOR + 2) /* to get 4.0 */ 143 #define PQF_MINUS_2 (PHI_Q_FACTOR - 2) /* to get 0.25 */ 144 #define PQF_PLUS_5_PLUS_2 (PQF_PLUS_5 + 2) 145 #define PQF_PLUS_5_MINUS_2 (PQF_PLUS_5 - 2) 146 147 #define MDP_CONVTP(tpVal) (((tpVal&0xF800)<<8)|((tpVal&0x7E0)<<5)|((tpVal&0x1F)<<3)) 148 149 #define MDPOP_ROTATION (MDPOP_ROT90|MDPOP_LR|MDPOP_UD) 150 #define MDP_CHKBIT(val, bit) ((bit) == ((val) & (bit))) 151 152 /* overlay interface API defines */ 153 typedef enum { 154 MORE_IBUF, 155 FINAL_IBUF, 156 COMPLETE_IBUF 157 } MDP_IBUF_STATE; 158 159 struct mdp_dirty_region { 160 __u32 xoffset; /* source origin in the x-axis */ 161 __u32 yoffset; /* source origin in the y-axis */ 162 __u32 width; /* number of pixels in the x-axis */ 163 __u32 height; /* number of pixels in the y-axis */ 164 }; 165 166 /* 167 * MDP extended data types 168 */ 169 typedef struct mdp_roi_s { 170 uint32 x; 171 uint32 y; 172 uint32 width; 173 uint32 height; 174 int32 lcd_x; 175 int32 lcd_y; 176 uint32 dst_width; 177 uint32 dst_height; 178 } MDP_ROI; 179 180 typedef struct mdp_ibuf_s { 181 uint8 *buf; 182 uint32 bpp; 183 uint32 ibuf_type; 184 uint32 ibuf_width; 185 uint32 ibuf_height; 186 187 MDP_ROI roi; 188 MDPIMG mdpImg; 189 190 int32 dma_x; 191 int32 dma_y; 192 uint32 dma_w; 193 uint32 dma_h; 194 195 uint32 vsync_enable; 196 uint32 visible_swapped; 197 } MDPIBUF; 198 199 struct mdp_dma_data { 200 boolean busy; 201 boolean waiting; 202 struct mutex ov_mutex; 203 struct semaphore mutex; 204 struct completion comp; 205 }; 206 207 #define MDP_CMD_DEBUG_ACCESS_BASE (MDP_BASE+0x10000) 208 209 #define MDP_DMA2_TERM 0x1 210 #define MDP_DMA3_TERM 0x2 211 #define MDP_PPP_TERM 0x4 212 #define MDP_DMA_S_TERM 0x8 213 #ifdef CONFIG_FB_MSM_MDP40 214 #define MDP_DMA_E_TERM 0x10 215 #define MDP_OVERLAY0_TERM 0x20 216 #define MDP_OVERLAY1_TERM 0x40 217 #endif 218 219 #define ACTIVE_START_X_EN BIT(31) 220 #define ACTIVE_START_Y_EN BIT(31) 221 #define ACTIVE_HIGH 0 222 #define ACTIVE_LOW 1 223 #define MDP_DMA_S_DONE BIT(2) 224 #define LCDC_FRAME_START BIT(15) 225 #define LCDC_UNDERFLOW BIT(16) 226 227 #ifdef CONFIG_FB_MSM_MDP22 228 #define MDP_DMA_P_DONE BIT(2) 229 #else 230 #define MDP_DMA_P_DONE BIT(14) 231 #endif 232 233 #define MDP_PPP_DONE BIT(0) 234 #define TV_OUT_DMA3_DONE BIT(6) 235 #define TV_ENC_UNDERRUN BIT(7) 236 #define TV_OUT_DMA3_START BIT(13) 237 #define MDP_HIST_DONE BIT(20) 238 239 #ifdef CONFIG_FB_MSM_MDP22 240 #define MDP_ANY_INTR_MASK (MDP_PPP_DONE| \ 241 MDP_DMA_P_DONE| \ 242 TV_ENC_UNDERRUN) 243 #else 244 #define MDP_ANY_INTR_MASK (MDP_PPP_DONE| \ 245 MDP_DMA_P_DONE| \ 246 MDP_DMA_S_DONE| \ 247 LCDC_UNDERFLOW| \ 248 MDP_HIST_DONE| \ 249 TV_ENC_UNDERRUN) 250 #endif 251 252 #define MDP_TOP_LUMA 16 253 #define MDP_TOP_CHROMA 0 254 #define MDP_BOTTOM_LUMA 19 255 #define MDP_BOTTOM_CHROMA 3 256 #define MDP_LEFT_LUMA 22 257 #define MDP_LEFT_CHROMA 6 258 #define MDP_RIGHT_LUMA 25 259 #define MDP_RIGHT_CHROMA 9 260 261 #define CLR_G 0x0 262 #define CLR_B 0x1 263 #define CLR_R 0x2 264 #define CLR_ALPHA 0x3 265 266 #define CLR_Y CLR_G 267 #define CLR_CB CLR_B 268 #define CLR_CR CLR_R 269 270 /* from lsb to msb */ 271 #define MDP_GET_PACK_PATTERN(a,x,y,z,bit) (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z)) 272 273 /* 274 * 0x0000 0x0004 0x0008 MDP sync config 275 */ 276 #ifdef CONFIG_FB_MSM_MDP22 277 #define MDP_SYNCFG_HGT_LOC 22 278 #define MDP_SYNCFG_VSYNC_EXT_EN BIT(21) 279 #define MDP_SYNCFG_VSYNC_INT_EN BIT(20) 280 #else 281 #define MDP_SYNCFG_HGT_LOC 21 282 #define MDP_SYNCFG_VSYNC_EXT_EN BIT(20) 283 #define MDP_SYNCFG_VSYNC_INT_EN BIT(19) 284 #define MDP_HW_VSYNC 285 #endif 286 287 /* 288 * 0x0018 MDP VSYNC THREASH 289 */ 290 #define MDP_PRIM_BELOW_LOC 0 291 #define MDP_PRIM_ABOVE_LOC 8 292 293 /* 294 * MDP_PRIMARY_VSYNC_OUT_CTRL 295 * 0x0080,84,88 internal vsync pulse config 296 */ 297 #define VSYNC_PULSE_EN BIT(31) 298 #define VSYNC_PULSE_INV BIT(30) 299 300 /* 301 * 0x008c MDP VSYNC CONTROL 302 */ 303 #define DISP0_VSYNC_MAP_VSYNC0 0 304 #define DISP0_VSYNC_MAP_VSYNC1 BIT(0) 305 #define DISP0_VSYNC_MAP_VSYNC2 BIT(0)|BIT(1) 306 307 #define DISP1_VSYNC_MAP_VSYNC0 0 308 #define DISP1_VSYNC_MAP_VSYNC1 BIT(2) 309 #define DISP1_VSYNC_MAP_VSYNC2 BIT(2)|BIT(3) 310 311 #define PRIMARY_LCD_SYNC_EN BIT(4) 312 #define PRIMARY_LCD_SYNC_DISABLE 0 313 314 #define SECONDARY_LCD_SYNC_EN BIT(5) 315 #define SECONDARY_LCD_SYNC_DISABLE 0 316 317 #define EXTERNAL_LCD_SYNC_EN BIT(6) 318 #define EXTERNAL_LCD_SYNC_DISABLE 0 319 320 /* 321 * 0x101f0 MDP VSYNC Threshold 322 */ 323 #define VSYNC_THRESHOLD_ABOVE_LOC 0 324 #define VSYNC_THRESHOLD_BELOW_LOC 16 325 #define VSYNC_ANTI_TEAR_EN BIT(31) 326 327 /* 328 * 0x10004 command config 329 */ 330 #define MDP_CMD_DBGBUS_EN BIT(0) 331 332 /* 333 * 0x10124 or 0x101d4PPP source config 334 */ 335 #define PPP_SRC_C0G_8BITS (BIT(1)|BIT(0)) 336 #define PPP_SRC_C1B_8BITS (BIT(3)|BIT(2)) 337 #define PPP_SRC_C2R_8BITS (BIT(5)|BIT(4)) 338 #define PPP_SRC_C3A_8BITS (BIT(7)|BIT(6)) 339 340 #define PPP_SRC_C0G_6BITS BIT(1) 341 #define PPP_SRC_C1B_6BITS BIT(3) 342 #define PPP_SRC_C2R_6BITS BIT(5) 343 344 #define PPP_SRC_C0G_5BITS BIT(0) 345 #define PPP_SRC_C1B_5BITS BIT(2) 346 #define PPP_SRC_C2R_5BITS BIT(4) 347 348 #define PPP_SRC_C3_ALPHA_EN BIT(8) 349 350 #define PPP_SRC_BPP_INTERLVD_1BYTES 0 351 #define PPP_SRC_BPP_INTERLVD_2BYTES BIT(9) 352 #define PPP_SRC_BPP_INTERLVD_3BYTES BIT(10) 353 #define PPP_SRC_BPP_INTERLVD_4BYTES (BIT(10)|BIT(9)) 354 355 #define PPP_SRC_BPP_ROI_ODD_X BIT(11) 356 #define PPP_SRC_BPP_ROI_ODD_Y BIT(12) 357 #define PPP_SRC_INTERLVD_2COMPONENTS BIT(13) 358 #define PPP_SRC_INTERLVD_3COMPONENTS BIT(14) 359 #define PPP_SRC_INTERLVD_4COMPONENTS (BIT(14)|BIT(13)) 360 361 /* 362 * RGB666 unpack format 363 * TIGHT means R6+G6+B6 together 364 * LOOSE means R6+2 +G6+2+ B6+2 (with MSB) 365 * or 2+R6 +2+G6 +2+B6 (with LSB) 366 */ 367 #define PPP_SRC_UNPACK_TIGHT BIT(17) 368 #define PPP_SRC_UNPACK_LOOSE 0 369 #define PPP_SRC_UNPACK_ALIGN_LSB 0 370 #define PPP_SRC_UNPACK_ALIGN_MSB BIT(18) 371 372 #define PPP_SRC_FETCH_PLANES_INTERLVD 0 373 #define PPP_SRC_FETCH_PLANES_PSEUDOPLNR BIT(20) 374 375 #define PPP_SRC_WMV9_MODE BIT(21) /* window media version 9 */ 376 377 /* 378 * 0x10138 PPP operation config 379 */ 380 #define PPP_OP_SCALE_X_ON BIT(0) 381 #define PPP_OP_SCALE_Y_ON BIT(1) 382 383 #define PPP_OP_CONVERT_RGB2YCBCR 0 384 #define PPP_OP_CONVERT_YCBCR2RGB BIT(2) 385 #define PPP_OP_CONVERT_ON BIT(3) 386 387 #define PPP_OP_CONVERT_MATRIX_PRIMARY 0 388 #define PPP_OP_CONVERT_MATRIX_SECONDARY BIT(4) 389 390 #define PPP_OP_LUT_C0_ON BIT(5) 391 #define PPP_OP_LUT_C1_ON BIT(6) 392 #define PPP_OP_LUT_C2_ON BIT(7) 393 394 /* rotate or blend enable */ 395 #define PPP_OP_ROT_ON BIT(8) 396 397 #define PPP_OP_ROT_90 BIT(9) 398 #define PPP_OP_FLIP_LR BIT(10) 399 #define PPP_OP_FLIP_UD BIT(11) 400 401 #define PPP_OP_BLEND_ON BIT(12) 402 403 #define PPP_OP_BLEND_SRCPIXEL_ALPHA 0 404 #define PPP_OP_BLEND_DSTPIXEL_ALPHA BIT(13) 405 #define PPP_OP_BLEND_CONSTANT_ALPHA BIT(14) 406 #define PPP_OP_BLEND_SRCPIXEL_TRANSP (BIT(13)|BIT(14)) 407 408 #define PPP_OP_BLEND_ALPHA_BLEND_NORMAL 0 409 #define PPP_OP_BLEND_ALPHA_BLEND_REVERSE BIT(15) 410 411 #define PPP_OP_DITHER_EN BIT(16) 412 413 #define PPP_OP_COLOR_SPACE_RGB 0 414 #define PPP_OP_COLOR_SPACE_YCBCR BIT(17) 415 416 #define PPP_OP_SRC_CHROMA_RGB 0 417 #define PPP_OP_SRC_CHROMA_H2V1 BIT(18) 418 #define PPP_OP_SRC_CHROMA_H1V2 BIT(19) 419 #define PPP_OP_SRC_CHROMA_420 (BIT(18)|BIT(19)) 420 #define PPP_OP_SRC_CHROMA_COSITE 0 421 #define PPP_OP_SRC_CHROMA_OFFSITE BIT(20) 422 423 #define PPP_OP_DST_CHROMA_RGB 0 424 #define PPP_OP_DST_CHROMA_H2V1 BIT(21) 425 #define PPP_OP_DST_CHROMA_H1V2 BIT(22) 426 #define PPP_OP_DST_CHROMA_420 (BIT(21)|BIT(22)) 427 #define PPP_OP_DST_CHROMA_COSITE 0 428 #define PPP_OP_DST_CHROMA_OFFSITE BIT(23) 429 430 #define PPP_BLEND_CALPHA_TRNASP BIT(24) 431 432 #define PPP_OP_BG_CHROMA_RGB 0 433 #define PPP_OP_BG_CHROMA_H2V1 BIT(25) 434 #define PPP_OP_BG_CHROMA_H1V2 BIT(26) 435 #define PPP_OP_BG_CHROMA_420 BIT(25)|BIT(26) 436 #define PPP_OP_BG_CHROMA_SITE_COSITE 0 437 #define PPP_OP_BG_CHROMA_SITE_OFFSITE BIT(27) 438 #define PPP_OP_DEINT_EN BIT(29) 439 440 #define PPP_BLEND_BG_USE_ALPHA_SEL (1 << 0) 441 #define PPP_BLEND_BG_ALPHA_REVERSE (1 << 3) 442 #define PPP_BLEND_BG_SRCPIXEL_ALPHA (0 << 1) 443 #define PPP_BLEND_BG_DSTPIXEL_ALPHA (1 << 1) 444 #define PPP_BLEND_BG_CONSTANT_ALPHA (2 << 1) 445 #define PPP_BLEND_BG_CONST_ALPHA_VAL(x) ((x) << 24) 446 447 #define PPP_OP_DST_RGB 0 448 #define PPP_OP_DST_YCBCR BIT(30) 449 /* 450 * 0x10150 PPP destination config 451 */ 452 #define PPP_DST_C0G_8BIT (BIT(0)|BIT(1)) 453 #define PPP_DST_C1B_8BIT (BIT(3)|BIT(2)) 454 #define PPP_DST_C2R_8BIT (BIT(5)|BIT(4)) 455 #define PPP_DST_C3A_8BIT (BIT(7)|BIT(6)) 456 457 #define PPP_DST_C0G_6BIT BIT(1) 458 #define PPP_DST_C1B_6BIT BIT(3) 459 #define PPP_DST_C2R_6BIT BIT(5) 460 461 #define PPP_DST_C0G_5BIT BIT(0) 462 #define PPP_DST_C1B_5BIT BIT(2) 463 #define PPP_DST_C2R_5BIT BIT(4) 464 465 #define PPP_DST_C3A_8BIT (BIT(7)|BIT(6)) 466 #define PPP_DST_C3ALPHA_EN BIT(8) 467 468 #define PPP_DST_PACKET_CNT_INTERLVD_2ELEM BIT(9) 469 #define PPP_DST_PACKET_CNT_INTERLVD_3ELEM BIT(10) 470 #define PPP_DST_PACKET_CNT_INTERLVD_4ELEM (BIT(10)|BIT(9)) 471 #define PPP_DST_PACKET_CNT_INTERLVD_6ELEM (BIT(11)|BIT(9)) 472 473 #define PPP_DST_PACK_LOOSE 0 474 #define PPP_DST_PACK_TIGHT BIT(13) 475 #define PPP_DST_PACK_ALIGN_LSB 0 476 #define PPP_DST_PACK_ALIGN_MSB BIT(14) 477 478 #define PPP_DST_OUT_SEL_AXI 0 479 #define PPP_DST_OUT_SEL_MDDI BIT(15) 480 481 #define PPP_DST_BPP_2BYTES BIT(16) 482 #define PPP_DST_BPP_3BYTES BIT(17) 483 #define PPP_DST_BPP_4BYTES (BIT(17)|BIT(16)) 484 485 #define PPP_DST_PLANE_INTERLVD 0 486 #define PPP_DST_PLANE_PLANAR BIT(18) 487 #define PPP_DST_PLANE_PSEUDOPLN BIT(19) 488 489 #define PPP_DST_TO_TV BIT(20) 490 491 #define PPP_DST_MDDI_PRIMARY 0 492 #define PPP_DST_MDDI_SECONDARY BIT(21) 493 #define PPP_DST_MDDI_EXTERNAL BIT(22) 494 495 /* 496 * 0x10180 DMA config 497 */ 498 #define DMA_DSTC0G_8BITS (BIT(1)|BIT(0)) 499 #define DMA_DSTC1B_8BITS (BIT(3)|BIT(2)) 500 #define DMA_DSTC2R_8BITS (BIT(5)|BIT(4)) 501 502 #define DMA_DSTC0G_6BITS BIT(1) 503 #define DMA_DSTC1B_6BITS BIT(3) 504 #define DMA_DSTC2R_6BITS BIT(5) 505 506 #define DMA_DSTC0G_5BITS BIT(0) 507 #define DMA_DSTC1B_5BITS BIT(2) 508 #define DMA_DSTC2R_5BITS BIT(4) 509 510 #define DMA_PACK_TIGHT BIT(6) 511 #define DMA_PACK_LOOSE 0 512 #define DMA_PACK_ALIGN_LSB 0 513 /* 514 * use DMA_PACK_ALIGN_MSB if the upper 6 bits from 8 bits output 515 * from LCDC block maps into 6 pins out to the panel 516 */ 517 #define DMA_PACK_ALIGN_MSB BIT(7) 518 #define DMA_PACK_PATTERN_RGB \ 519 (MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 2)<<8) 520 #define DMA_PACK_PATTERN_BGR \ 521 (MDP_GET_PACK_PATTERN(0, CLR_B, CLR_G, CLR_R, 2)<<8) 522 #define DMA_OUT_SEL_AHB 0 523 #define DMA_OUT_SEL_LCDC BIT(20) 524 #define DMA_IBUF_FORMAT_RGB888 0 525 #define DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888 BIT(26) 526 527 #ifdef CONFIG_FB_MSM_MDP22 528 #define DMA_OUT_SEL_MDDI BIT(14) 529 #define DMA_AHBM_LCD_SEL_PRIMARY 0 530 #define DMA_AHBM_LCD_SEL_SECONDARY BIT(15) 531 #define DMA_IBUF_C3ALPHA_EN BIT(16) 532 #define DMA_DITHER_EN BIT(17) 533 #define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0 534 #define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY BIT(18) 535 #define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL BIT(19) 536 #define DMA_IBUF_FORMAT_RGB565 BIT(20) 537 #define DMA_IBUF_FORMAT_RGB888_OR_ARGB8888 0 538 #define DMA_IBUF_NONCONTIGUOUS BIT(21) 539 #else 540 #define DMA_OUT_SEL_MDDI BIT(19) 541 #define DMA_AHBM_LCD_SEL_PRIMARY 0 542 #define DMA_AHBM_LCD_SEL_SECONDARY 0 543 #define DMA_IBUF_C3ALPHA_EN 0 544 #define DMA_DITHER_EN BIT(24) 545 #define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0 546 #define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY 0 547 #define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL 0 548 #define DMA_IBUF_FORMAT_RGB565 BIT(25) 549 #define DMA_IBUF_NONCONTIGUOUS 0 550 #endif 551 552 /* 553 * MDDI Register 554 */ 555 #define MDDI_VDO_PACKET_DESC 0x5666 556 557 #ifdef CONFIG_FB_MSM_MDP40 558 #define MDP_INTR_ENABLE (msm_mdp_base + 0x0050) 559 #define MDP_INTR_STATUS (msm_mdp_base + 0x0054) 560 #define MDP_INTR_CLEAR (msm_mdp_base + 0x0058) 561 #define MDP_EBI2_LCD0 (msm_mdp_base + 0x0060) 562 #define MDP_EBI2_LCD1 (msm_mdp_base + 0x0064) 563 #define MDP_EBI2_PORTMAP_MODE (msm_mdp_base + 0x0070) 564 565 #define MDP_DMA_P_HIST_INTR_STATUS (msm_mdp_base + 0x95014) 566 #define MDP_DMA_P_HIST_INTR_CLEAR (msm_mdp_base + 0x95018) 567 #define MDP_DMA_P_HIST_INTR_ENABLE (msm_mdp_base + 0x9501C) 568 #else 569 #define MDP_INTR_ENABLE (msm_mdp_base + 0x0020) 570 #define MDP_INTR_STATUS (msm_mdp_base + 0x0024) 571 #define MDP_INTR_CLEAR (msm_mdp_base + 0x0028) 572 #define MDP_EBI2_LCD0 (msm_mdp_base + 0x003c) 573 #define MDP_EBI2_LCD1 (msm_mdp_base + 0x0040) 574 #define MDP_EBI2_PORTMAP_MODE (msm_mdp_base + 0x005c) 575 #endif 576 577 #define MDP_FULL_BYPASS_WORD43 (msm_mdp_base + 0x101ac) 578 579 #define MDP_CSC_PFMVn(n) (msm_mdp_base + 0x40400 + 4 * (n)) 580 #define MDP_CSC_PRMVn(n) (msm_mdp_base + 0x40440 + 4 * (n)) 581 #define MDP_CSC_PRE_BV1n(n) (msm_mdp_base + 0x40500 + 4 * (n)) 582 #define MDP_CSC_PRE_BV2n(n) (msm_mdp_base + 0x40540 + 4 * (n)) 583 #define MDP_CSC_POST_BV1n(n) (msm_mdp_base + 0x40580 + 4 * (n)) 584 #define MDP_CSC_POST_BV2n(n) (msm_mdp_base + 0x405c0 + 4 * (n)) 585 586 #ifdef CONFIG_FB_MSM_MDP31 587 #define MDP_CSC_PRE_LV1n(n) (msm_mdp_base + 0x40600 + 4 * (n)) 588 #define MDP_CSC_PRE_LV2n(n) (msm_mdp_base + 0x40640 + 4 * (n)) 589 #define MDP_CSC_POST_LV1n(n) (msm_mdp_base + 0x40680 + 4 * (n)) 590 #define MDP_CSC_POST_LV2n(n) (msm_mdp_base + 0x406c0 + 4 * (n)) 591 #define MDP_PPP_SCALE_COEFF_LSBn(n) (msm_mdp_base + 0x50400 + 8 * (n)) 592 #define MDP_PPP_SCALE_COEFF_MSBn(n) (msm_mdp_base + 0x50404 + 8 * (n)) 593 594 #define SCALE_D0_SET 0 595 #define SCALE_D1_SET BIT(0) 596 #define SCALE_D2_SET BIT(1) 597 #define SCALE_U1_SET (BIT(0)|BIT(1)) 598 599 #else 600 #define MDP_CSC_PRE_LV1n(n) (msm_mdp_base + 0x40580 + 4 * (n)) 601 #endif 602 603 #define MDP_CURSOR_WIDTH 64 604 #define MDP_CURSOR_HEIGHT 64 605 #define MDP_CURSOR_SIZE (MDP_CURSOR_WIDTH*MDP_CURSOR_WIDTH*4) 606 607 #define MDP_DMA_P_LUT_C0_EN BIT(0) 608 #define MDP_DMA_P_LUT_C1_EN BIT(1) 609 #define MDP_DMA_P_LUT_C2_EN BIT(2) 610 #define MDP_DMA_P_LUT_POST BIT(4) 611 612 void mdp_hw_init(void); 613 int mdp_ppp_pipe_wait(void); 614 void mdp_pipe_kickoff(uint32 term, struct msm_fb_data_type *mfd); 615 void mdp_pipe_ctrl(MDP_BLOCK_TYPE block, MDP_BLOCK_POWER_STATE state, 616 boolean isr); 617 void mdp_set_dma_pan_info(struct fb_info *info, struct mdp_dirty_region *dirty, 618 boolean sync); 619 void mdp_dma_pan_update(struct fb_info *info); 620 void mdp_refresh_screen(unsigned long data); 621 int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req, 622 struct file **pp_src, struct file **pp_dest); 623 void mdp_lcd_update_workqueue_handler(struct work_struct *work); 624 void mdp_vsync_resync_workqueue_handler(struct work_struct *work); 625 void mdp_dma2_update(struct msm_fb_data_type *mfd); 626 void mdp_config_vsync(struct msm_fb_data_type *); 627 uint32 mdp_get_lcd_line_counter(struct msm_fb_data_type *mfd); 628 enum hrtimer_restart mdp_dma2_vsync_hrtimer_handler(struct hrtimer *ht); 629 void mdp_set_scale(MDPIBUF *iBuf, 630 uint32 dst_roi_width, 631 uint32 dst_roi_height, 632 boolean inputRGB, boolean outputRGB, uint32 *pppop_reg_ptr); 633 void mdp_init_scale_table(void); 634 void mdp_adjust_start_addr(uint8 **src0, 635 uint8 **src1, 636 int v_slice, 637 int h_slice, 638 int x, 639 int y, 640 uint32 width, 641 uint32 height, int bpp, MDPIBUF *iBuf, int layer); 642 void mdp_set_blend_attr(MDPIBUF *iBuf, 643 uint32 *alpha, 644 uint32 *tpVal, 645 uint32 perPixelAlpha, uint32 *pppop_reg_ptr); 646 647 int mdp_dma3_on(struct platform_device *pdev); 648 int mdp_dma3_off(struct platform_device *pdev); 649 void mdp_dma3_update(struct msm_fb_data_type *mfd); 650 651 int mdp_lcdc_on(struct platform_device *pdev); 652 int mdp_lcdc_off(struct platform_device *pdev); 653 void mdp_lcdc_update(struct msm_fb_data_type *mfd); 654 int mdp_hw_cursor_update(struct fb_info *info, struct fb_cursor *cursor); 655 void mdp_enable_irq(uint32 term); 656 void mdp_disable_irq(uint32 term); 657 void mdp_disable_irq_nolock(uint32 term); 658 uint32_t mdp_get_bytes_per_pixel(uint32_t format); 659 660 #ifdef MDP_HW_VSYNC 661 void mdp_hw_vsync_clk_enable(struct msm_fb_data_type *mfd); 662 void mdp_hw_vsync_clk_disable(struct msm_fb_data_type *mfd); 663 #endif 664 665 void mdp_dma_s_update(struct msm_fb_data_type *mfd); 666 667 /* Added to support flipping */ 668 void mdp_set_offset_info(struct fb_info *info, uint32 address, uint32 interval); 669 670 int get_gem_img(struct mdp_img *img, unsigned long *start, 671 unsigned long *len); 672 int get_img(struct mdp_img *img, struct fb_info *info, 673 unsigned long *start, unsigned long *len, 674 struct file **pp_file); 675 676 677 /*int get_img(struct msmfb_data *img, struct fb_info *info, 678 unsigned long *start, unsigned long *len, struct file **pp_file);*/ 679 #endif /* MDP_H */ 680