1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2009-2011 LSI Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 * FILE: megaraid_sas_fusion.h 21 * 22 * Authors: LSI Corporation 23 * Manoj Jose 24 * Sumant Patro 25 * 26 * Send feedback to: <megaraidlinux@lsi.com> 27 * 28 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 29 * ATTN: Linuxraid 30 */ 31 32 #ifndef _MEGARAID_SAS_FUSION_H_ 33 #define _MEGARAID_SAS_FUSION_H_ 34 35 /* Fusion defines */ 36 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 37 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 38 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 39 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 40 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 41 #define MEGASAS_LOAD_BALANCE_FLAG 0x1 42 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1 43 #define HOST_DIAG_WRITE_ENABLE 0x80 44 #define HOST_DIAG_RESET_ADAPTER 0x4 45 #define MEGASAS_FUSION_MAX_RESET_TRIES 3 46 47 /* T10 PI defines */ 48 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 49 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 50 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9 51 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB 52 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18 53 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20 54 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60 55 #define MEGASAS_EEDPBLOCKSIZE 512 56 57 /* 58 * Raid context flags 59 */ 60 61 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 62 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 63 enum MR_RAID_FLAGS_IO_SUB_TYPE { 64 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 65 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 66 }; 67 68 /* 69 * Request descriptor types 70 */ 71 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 72 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1 73 74 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 75 76 #define MEGASAS_FP_CMD_LEN 16 77 #define MEGASAS_FUSION_IN_RESET 0 78 79 /* 80 * Raid Context structure which describes MegaRAID specific IO Paramenters 81 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 82 */ 83 84 struct RAID_CONTEXT { 85 u16 resvd0; 86 u16 timeoutValue; 87 u8 regLockFlags; 88 u8 resvd1; 89 u16 VirtualDiskTgtId; 90 u64 regLockRowLBA; 91 u32 regLockLength; 92 u16 nextLMId; 93 u8 exStatus; 94 u8 status; 95 u8 RAIDFlags; 96 u8 numSGE; 97 u16 configSeqNum; 98 u8 spanArm; 99 u8 resvd2[3]; 100 }; 101 102 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 103 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 104 105 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 106 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 107 108 /* 109 * define region lock types 110 */ 111 enum REGION_TYPE { 112 REGION_TYPE_UNUSED = 0, 113 REGION_TYPE_SHARED_READ = 1, 114 REGION_TYPE_SHARED_WRITE = 2, 115 REGION_TYPE_EXCLUSIVE = 3, 116 }; 117 118 /* MPI2 defines */ 119 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 120 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 121 #define MPI2_VERSION_MAJOR (0x02) 122 #define MPI2_VERSION_MINOR (0x00) 123 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 124 #define MPI2_VERSION_MAJOR_SHIFT (8) 125 #define MPI2_VERSION_MINOR_MASK (0x00FF) 126 #define MPI2_VERSION_MINOR_SHIFT (0) 127 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 128 MPI2_VERSION_MINOR) 129 #define MPI2_HEADER_VERSION_UNIT (0x10) 130 #define MPI2_HEADER_VERSION_DEV (0x00) 131 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 132 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 133 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 134 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 135 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 136 MPI2_HEADER_VERSION_DEV) 137 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 138 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 139 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 140 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 141 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 142 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 143 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 144 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 145 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 146 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 147 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 148 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 149 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 150 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 151 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 152 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 153 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 154 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 155 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 156 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 157 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 158 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 159 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 160 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 161 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 162 163 struct MPI25_IEEE_SGE_CHAIN64 { 164 u64 Address; 165 u32 Length; 166 u16 Reserved1; 167 u8 NextChainOffset; 168 u8 Flags; 169 }; 170 171 struct MPI2_SGE_SIMPLE_UNION { 172 u32 FlagsLength; 173 union { 174 u32 Address32; 175 u64 Address64; 176 } u; 177 }; 178 179 struct MPI2_SCSI_IO_CDB_EEDP32 { 180 u8 CDB[20]; /* 0x00 */ 181 u32 PrimaryReferenceTag; /* 0x14 */ 182 u16 PrimaryApplicationTag; /* 0x18 */ 183 u16 PrimaryApplicationTagMask; /* 0x1A */ 184 u32 TransferLength; /* 0x1C */ 185 }; 186 187 struct MPI2_SGE_CHAIN_UNION { 188 u16 Length; 189 u8 NextChainOffset; 190 u8 Flags; 191 union { 192 u32 Address32; 193 u64 Address64; 194 } u; 195 }; 196 197 struct MPI2_IEEE_SGE_SIMPLE32 { 198 u32 Address; 199 u32 FlagsLength; 200 }; 201 202 struct MPI2_IEEE_SGE_CHAIN32 { 203 u32 Address; 204 u32 FlagsLength; 205 }; 206 207 struct MPI2_IEEE_SGE_SIMPLE64 { 208 u64 Address; 209 u32 Length; 210 u16 Reserved1; 211 u8 Reserved2; 212 u8 Flags; 213 }; 214 215 struct MPI2_IEEE_SGE_CHAIN64 { 216 u64 Address; 217 u32 Length; 218 u16 Reserved1; 219 u8 Reserved2; 220 u8 Flags; 221 }; 222 223 union MPI2_IEEE_SGE_SIMPLE_UNION { 224 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 225 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 226 }; 227 228 union MPI2_IEEE_SGE_CHAIN_UNION { 229 struct MPI2_IEEE_SGE_CHAIN32 Chain32; 230 struct MPI2_IEEE_SGE_CHAIN64 Chain64; 231 }; 232 233 union MPI2_SGE_IO_UNION { 234 struct MPI2_SGE_SIMPLE_UNION MpiSimple; 235 struct MPI2_SGE_CHAIN_UNION MpiChain; 236 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 237 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 238 }; 239 240 union MPI2_SCSI_IO_CDB_UNION { 241 u8 CDB32[32]; 242 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 243 struct MPI2_SGE_SIMPLE_UNION SGE; 244 }; 245 246 /* 247 * RAID SCSI IO Request Message 248 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 249 */ 250 struct MPI2_RAID_SCSI_IO_REQUEST { 251 u16 DevHandle; /* 0x00 */ 252 u8 ChainOffset; /* 0x02 */ 253 u8 Function; /* 0x03 */ 254 u16 Reserved1; /* 0x04 */ 255 u8 Reserved2; /* 0x06 */ 256 u8 MsgFlags; /* 0x07 */ 257 u8 VP_ID; /* 0x08 */ 258 u8 VF_ID; /* 0x09 */ 259 u16 Reserved3; /* 0x0A */ 260 u32 SenseBufferLowAddress; /* 0x0C */ 261 u16 SGLFlags; /* 0x10 */ 262 u8 SenseBufferLength; /* 0x12 */ 263 u8 Reserved4; /* 0x13 */ 264 u8 SGLOffset0; /* 0x14 */ 265 u8 SGLOffset1; /* 0x15 */ 266 u8 SGLOffset2; /* 0x16 */ 267 u8 SGLOffset3; /* 0x17 */ 268 u32 SkipCount; /* 0x18 */ 269 u32 DataLength; /* 0x1C */ 270 u32 BidirectionalDataLength; /* 0x20 */ 271 u16 IoFlags; /* 0x24 */ 272 u16 EEDPFlags; /* 0x26 */ 273 u32 EEDPBlockSize; /* 0x28 */ 274 u32 SecondaryReferenceTag; /* 0x2C */ 275 u16 SecondaryApplicationTag; /* 0x30 */ 276 u16 ApplicationTagTranslationMask; /* 0x32 */ 277 u8 LUN[8]; /* 0x34 */ 278 u32 Control; /* 0x3C */ 279 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 280 struct RAID_CONTEXT RaidContext; /* 0x60 */ 281 union MPI2_SGE_IO_UNION SGL; /* 0x80 */ 282 }; 283 284 /* 285 * MPT RAID MFA IO Descriptor. 286 */ 287 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR { 288 u32 RequestFlags:8; 289 u32 MessageAddress1:24; /* bits 31:8*/ 290 u32 MessageAddress2; /* bits 61:32 */ 291 }; 292 293 /* Default Request Descriptor */ 294 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR { 295 u8 RequestFlags; /* 0x00 */ 296 u8 MSIxIndex; /* 0x01 */ 297 u16 SMID; /* 0x02 */ 298 u16 LMID; /* 0x04 */ 299 u16 DescriptorTypeDependent; /* 0x06 */ 300 }; 301 302 /* High Priority Request Descriptor */ 303 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 304 u8 RequestFlags; /* 0x00 */ 305 u8 MSIxIndex; /* 0x01 */ 306 u16 SMID; /* 0x02 */ 307 u16 LMID; /* 0x04 */ 308 u16 Reserved1; /* 0x06 */ 309 }; 310 311 /* SCSI IO Request Descriptor */ 312 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 313 u8 RequestFlags; /* 0x00 */ 314 u8 MSIxIndex; /* 0x01 */ 315 u16 SMID; /* 0x02 */ 316 u16 LMID; /* 0x04 */ 317 u16 DevHandle; /* 0x06 */ 318 }; 319 320 /* SCSI Target Request Descriptor */ 321 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 322 u8 RequestFlags; /* 0x00 */ 323 u8 MSIxIndex; /* 0x01 */ 324 u16 SMID; /* 0x02 */ 325 u16 LMID; /* 0x04 */ 326 u16 IoIndex; /* 0x06 */ 327 }; 328 329 /* RAID Accelerator Request Descriptor */ 330 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 331 u8 RequestFlags; /* 0x00 */ 332 u8 MSIxIndex; /* 0x01 */ 333 u16 SMID; /* 0x02 */ 334 u16 LMID; /* 0x04 */ 335 u16 Reserved; /* 0x06 */ 336 }; 337 338 /* union of Request Descriptors */ 339 union MEGASAS_REQUEST_DESCRIPTOR_UNION { 340 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 341 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 342 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 343 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 344 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 345 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 346 union { 347 struct { 348 u32 low; 349 u32 high; 350 } u; 351 u64 Words; 352 }; 353 }; 354 355 /* Default Reply Descriptor */ 356 struct MPI2_DEFAULT_REPLY_DESCRIPTOR { 357 u8 ReplyFlags; /* 0x00 */ 358 u8 MSIxIndex; /* 0x01 */ 359 u16 DescriptorTypeDependent1; /* 0x02 */ 360 u32 DescriptorTypeDependent2; /* 0x04 */ 361 }; 362 363 /* Address Reply Descriptor */ 364 struct MPI2_ADDRESS_REPLY_DESCRIPTOR { 365 u8 ReplyFlags; /* 0x00 */ 366 u8 MSIxIndex; /* 0x01 */ 367 u16 SMID; /* 0x02 */ 368 u32 ReplyFrameAddress; /* 0x04 */ 369 }; 370 371 /* SCSI IO Success Reply Descriptor */ 372 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 373 u8 ReplyFlags; /* 0x00 */ 374 u8 MSIxIndex; /* 0x01 */ 375 u16 SMID; /* 0x02 */ 376 u16 TaskTag; /* 0x04 */ 377 u16 Reserved1; /* 0x06 */ 378 }; 379 380 /* TargetAssist Success Reply Descriptor */ 381 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 382 u8 ReplyFlags; /* 0x00 */ 383 u8 MSIxIndex; /* 0x01 */ 384 u16 SMID; /* 0x02 */ 385 u8 SequenceNumber; /* 0x04 */ 386 u8 Reserved1; /* 0x05 */ 387 u16 IoIndex; /* 0x06 */ 388 }; 389 390 /* Target Command Buffer Reply Descriptor */ 391 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 392 u8 ReplyFlags; /* 0x00 */ 393 u8 MSIxIndex; /* 0x01 */ 394 u8 VP_ID; /* 0x02 */ 395 u8 Flags; /* 0x03 */ 396 u16 InitiatorDevHandle; /* 0x04 */ 397 u16 IoIndex; /* 0x06 */ 398 }; 399 400 /* RAID Accelerator Success Reply Descriptor */ 401 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 402 u8 ReplyFlags; /* 0x00 */ 403 u8 MSIxIndex; /* 0x01 */ 404 u16 SMID; /* 0x02 */ 405 u32 Reserved; /* 0x04 */ 406 }; 407 408 /* union of Reply Descriptors */ 409 union MPI2_REPLY_DESCRIPTORS_UNION { 410 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 411 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 412 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 413 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 414 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 415 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 416 RAIDAcceleratorSuccess; 417 u64 Words; 418 }; 419 420 /* IOCInit Request message */ 421 struct MPI2_IOC_INIT_REQUEST { 422 u8 WhoInit; /* 0x00 */ 423 u8 Reserved1; /* 0x01 */ 424 u8 ChainOffset; /* 0x02 */ 425 u8 Function; /* 0x03 */ 426 u16 Reserved2; /* 0x04 */ 427 u8 Reserved3; /* 0x06 */ 428 u8 MsgFlags; /* 0x07 */ 429 u8 VP_ID; /* 0x08 */ 430 u8 VF_ID; /* 0x09 */ 431 u16 Reserved4; /* 0x0A */ 432 u16 MsgVersion; /* 0x0C */ 433 u16 HeaderVersion; /* 0x0E */ 434 u32 Reserved5; /* 0x10 */ 435 u16 Reserved6; /* 0x14 */ 436 u8 Reserved7; /* 0x16 */ 437 u8 HostMSIxVectors; /* 0x17 */ 438 u16 Reserved8; /* 0x18 */ 439 u16 SystemRequestFrameSize; /* 0x1A */ 440 u16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 441 u16 ReplyFreeQueueDepth; /* 0x1E */ 442 u32 SenseBufferAddressHigh; /* 0x20 */ 443 u32 SystemReplyAddressHigh; /* 0x24 */ 444 u64 SystemRequestFrameBaseAddress; /* 0x28 */ 445 u64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 446 u64 ReplyFreeQueueAddress; /* 0x38 */ 447 u64 TimeStamp; /* 0x40 */ 448 }; 449 450 /* mrpriv defines */ 451 #define MR_PD_INVALID 0xFFFF 452 #define MAX_SPAN_DEPTH 8 453 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 454 #define MAX_ROW_SIZE 32 455 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 456 #define MAX_LOGICAL_DRIVES 64 457 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 458 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 459 #define MAX_ARRAYS 128 460 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 461 #define MAX_PHYSICAL_DEVICES 256 462 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 463 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 464 465 struct MR_DEV_HANDLE_INFO { 466 u16 curDevHdl; 467 u8 validHandles; 468 u8 reserved; 469 u16 devHandle[2]; 470 }; 471 472 struct MR_ARRAY_INFO { 473 u16 pd[MAX_RAIDMAP_ROW_SIZE]; 474 }; 475 476 struct MR_QUAD_ELEMENT { 477 u64 logStart; 478 u64 logEnd; 479 u64 offsetInSpan; 480 u32 diff; 481 u32 reserved1; 482 }; 483 484 struct MR_SPAN_INFO { 485 u32 noElements; 486 u32 reserved1; 487 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 488 }; 489 490 struct MR_LD_SPAN { 491 u64 startBlk; 492 u64 numBlks; 493 u16 arrayRef; 494 u8 reserved[6]; 495 }; 496 497 struct MR_SPAN_BLOCK_INFO { 498 u64 num_rows; 499 struct MR_LD_SPAN span; 500 struct MR_SPAN_INFO block_span_info; 501 }; 502 503 struct MR_LD_RAID { 504 struct { 505 u32 fpCapable:1; 506 u32 reserved5:3; 507 u32 ldPiMode:4; 508 u32 pdPiMode:4; 509 u32 encryptionType:8; 510 u32 fpWriteCapable:1; 511 u32 fpReadCapable:1; 512 u32 fpWriteAcrossStripe:1; 513 u32 fpReadAcrossStripe:1; 514 u32 reserved4:8; 515 } capability; 516 u32 reserved6; 517 u64 size; 518 u8 spanDepth; 519 u8 level; 520 u8 stripeShift; 521 u8 rowSize; 522 u8 rowDataSize; 523 u8 writeMode; 524 u8 PRL; 525 u8 SRL; 526 u16 targetId; 527 u8 ldState; 528 u8 regTypeReqOnWrite; 529 u8 modFactor; 530 u8 reserved2[1]; 531 u16 seqNum; 532 533 struct { 534 u32 ldSyncRequired:1; 535 u32 reserved:31; 536 } flags; 537 538 u8 reserved3[0x5C]; 539 }; 540 541 struct MR_LD_SPAN_MAP { 542 struct MR_LD_RAID ldRaid; 543 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 544 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 545 }; 546 547 struct MR_FW_RAID_MAP { 548 u32 totalSize; 549 union { 550 struct { 551 u32 maxLd; 552 u32 maxSpanDepth; 553 u32 maxRowSize; 554 u32 maxPdCount; 555 u32 maxArrays; 556 } validationInfo; 557 u32 version[5]; 558 u32 reserved1[5]; 559 }; 560 561 u32 ldCount; 562 u32 Reserved1; 563 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ 564 MAX_RAIDMAP_VIEWS]; 565 u8 fpPdIoTimeoutSec; 566 u8 reserved2[7]; 567 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 568 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 569 struct MR_LD_SPAN_MAP ldSpanMap[1]; 570 }; 571 572 struct IO_REQUEST_INFO { 573 u64 ldStartBlock; 574 u32 numBlocks; 575 u16 ldTgtId; 576 u8 isRead; 577 u16 devHandle; 578 u64 pdBlock; 579 u8 fpOkForIo; 580 }; 581 582 struct MR_LD_TARGET_SYNC { 583 u8 targetId; 584 u8 reserved; 585 u16 seqNum; 586 }; 587 588 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 589 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 590 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 591 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 592 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 593 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 594 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 595 596 struct megasas_register_set; 597 struct megasas_instance; 598 599 union desc_word { 600 u64 word; 601 struct { 602 u32 low; 603 u32 high; 604 } u; 605 }; 606 607 struct megasas_cmd_fusion { 608 struct MPI2_RAID_SCSI_IO_REQUEST *io_request; 609 dma_addr_t io_request_phys_addr; 610 611 union MPI2_SGE_IO_UNION *sg_frame; 612 dma_addr_t sg_frame_phys_addr; 613 614 u8 *sense; 615 dma_addr_t sense_phys_addr; 616 617 struct list_head list; 618 struct scsi_cmnd *scmd; 619 struct megasas_instance *instance; 620 621 u8 retry_for_fw_reset; 622 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc; 623 624 /* 625 * Context for a MFI frame. 626 * Used to get the mfi cmd from list when a MFI cmd is completed 627 */ 628 u32 sync_cmd_idx; 629 u32 index; 630 u8 flags; 631 }; 632 633 struct LD_LOAD_BALANCE_INFO { 634 u8 loadBalanceFlag; 635 u8 reserved1; 636 u16 raid1DevHandle[2]; 637 atomic_t scsi_pending_cmds[2]; 638 u64 last_accessed_block[2]; 639 }; 640 641 struct MR_FW_RAID_MAP_ALL { 642 struct MR_FW_RAID_MAP raidMap; 643 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 644 } __attribute__ ((packed)); 645 646 struct fusion_context { 647 struct megasas_cmd_fusion **cmd_list; 648 struct list_head cmd_pool; 649 650 spinlock_t cmd_pool_lock; 651 652 dma_addr_t req_frames_desc_phys; 653 u8 *req_frames_desc; 654 655 struct dma_pool *io_request_frames_pool; 656 dma_addr_t io_request_frames_phys; 657 u8 *io_request_frames; 658 659 struct dma_pool *sg_dma_pool; 660 struct dma_pool *sense_dma_pool; 661 662 dma_addr_t reply_frames_desc_phys; 663 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc; 664 struct dma_pool *reply_frames_desc_pool; 665 666 u16 last_reply_idx; 667 668 u32 reply_q_depth; 669 u32 request_alloc_sz; 670 u32 reply_alloc_sz; 671 u32 io_frames_alloc_sz; 672 673 u16 max_sge_in_main_msg; 674 u16 max_sge_in_chain; 675 676 u8 chain_offset_io_request; 677 u8 chain_offset_mfi_pthru; 678 679 struct MR_FW_RAID_MAP_ALL *ld_map[2]; 680 dma_addr_t ld_map_phys[2]; 681 682 u32 map_sz; 683 u8 fast_path_io; 684 struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES]; 685 }; 686 687 union desc_value { 688 u64 word; 689 struct { 690 u32 low; 691 u32 high; 692 } u; 693 }; 694 695 #endif /* _MEGARAID_SAS_FUSION_H_ */ 696