1 2 /* 3 * bfi_ctreg.h catapult host block register definitions 4 * 5 * !!! Do not edit. Auto generated. !!! 6 */ 7 8 #ifndef __BFI_CTREG_H__ 9 #define __BFI_CTREG_H__ 10 11 12 #define HOSTFN0_LPU_MBOX0_0 0x00019200 13 #define HOSTFN1_LPU_MBOX0_8 0x00019260 14 #define LPU_HOSTFN0_MBOX0_0 0x00019280 15 #define LPU_HOSTFN1_MBOX0_8 0x000192e0 16 #define HOSTFN2_LPU_MBOX0_0 0x00019400 17 #define HOSTFN3_LPU_MBOX0_8 0x00019460 18 #define LPU_HOSTFN2_MBOX0_0 0x00019480 19 #define LPU_HOSTFN3_MBOX0_8 0x000194e0 20 #define HOSTFN0_INT_STATUS 0x00014000 21 #define __HOSTFN0_HALT_OCCURRED 0x01000000 22 #define __HOSTFN0_INT_STATUS_LVL_MK 0x00f00000 23 #define __HOSTFN0_INT_STATUS_LVL_SH 20 24 #define __HOSTFN0_INT_STATUS_LVL(_v) ((_v) << __HOSTFN0_INT_STATUS_LVL_SH) 25 #define __HOSTFN0_INT_STATUS_P_MK 0x000f0000 26 #define __HOSTFN0_INT_STATUS_P_SH 16 27 #define __HOSTFN0_INT_STATUS_P(_v) ((_v) << __HOSTFN0_INT_STATUS_P_SH) 28 #define __HOSTFN0_INT_STATUS_F 0x0000ffff 29 #define HOSTFN0_INT_MSK 0x00014004 30 #define HOST_PAGE_NUM_FN0 0x00014008 31 #define __HOST_PAGE_NUM_FN 0x000001ff 32 #define HOST_MSIX_ERR_INDEX_FN0 0x0001400c 33 #define __MSIX_ERR_INDEX_FN 0x000001ff 34 #define HOSTFN1_INT_STATUS 0x00014100 35 #define __HOSTFN1_HALT_OCCURRED 0x01000000 36 #define __HOSTFN1_INT_STATUS_LVL_MK 0x00f00000 37 #define __HOSTFN1_INT_STATUS_LVL_SH 20 38 #define __HOSTFN1_INT_STATUS_LVL(_v) ((_v) << __HOSTFN1_INT_STATUS_LVL_SH) 39 #define __HOSTFN1_INT_STATUS_P_MK 0x000f0000 40 #define __HOSTFN1_INT_STATUS_P_SH 16 41 #define __HOSTFN1_INT_STATUS_P(_v) ((_v) << __HOSTFN1_INT_STATUS_P_SH) 42 #define __HOSTFN1_INT_STATUS_F 0x0000ffff 43 #define HOSTFN1_INT_MSK 0x00014104 44 #define HOST_PAGE_NUM_FN1 0x00014108 45 #define HOST_MSIX_ERR_INDEX_FN1 0x0001410c 46 #define APP_PLL_425_CTL_REG 0x00014204 47 #define __P_425_PLL_LOCK 0x80000000 48 #define __APP_PLL_425_SRAM_USE_100MHZ 0x00100000 49 #define __APP_PLL_425_RESET_TIMER_MK 0x000e0000 50 #define __APP_PLL_425_RESET_TIMER_SH 17 51 #define __APP_PLL_425_RESET_TIMER(_v) ((_v) << __APP_PLL_425_RESET_TIMER_SH) 52 #define __APP_PLL_425_LOGIC_SOFT_RESET 0x00010000 53 #define __APP_PLL_425_CNTLMT0_1_MK 0x0000c000 54 #define __APP_PLL_425_CNTLMT0_1_SH 14 55 #define __APP_PLL_425_CNTLMT0_1(_v) ((_v) << __APP_PLL_425_CNTLMT0_1_SH) 56 #define __APP_PLL_425_JITLMT0_1_MK 0x00003000 57 #define __APP_PLL_425_JITLMT0_1_SH 12 58 #define __APP_PLL_425_JITLMT0_1(_v) ((_v) << __APP_PLL_425_JITLMT0_1_SH) 59 #define __APP_PLL_425_HREF 0x00000800 60 #define __APP_PLL_425_HDIV 0x00000400 61 #define __APP_PLL_425_P0_1_MK 0x00000300 62 #define __APP_PLL_425_P0_1_SH 8 63 #define __APP_PLL_425_P0_1(_v) ((_v) << __APP_PLL_425_P0_1_SH) 64 #define __APP_PLL_425_Z0_2_MK 0x000000e0 65 #define __APP_PLL_425_Z0_2_SH 5 66 #define __APP_PLL_425_Z0_2(_v) ((_v) << __APP_PLL_425_Z0_2_SH) 67 #define __APP_PLL_425_RSEL200500 0x00000010 68 #define __APP_PLL_425_ENARST 0x00000008 69 #define __APP_PLL_425_BYPASS 0x00000004 70 #define __APP_PLL_425_LRESETN 0x00000002 71 #define __APP_PLL_425_ENABLE 0x00000001 72 #define APP_PLL_312_CTL_REG 0x00014208 73 #define __P_312_PLL_LOCK 0x80000000 74 #define __ENABLE_MAC_AHB_1 0x00800000 75 #define __ENABLE_MAC_AHB_0 0x00400000 76 #define __ENABLE_MAC_1 0x00200000 77 #define __ENABLE_MAC_0 0x00100000 78 #define __APP_PLL_312_RESET_TIMER_MK 0x000e0000 79 #define __APP_PLL_312_RESET_TIMER_SH 17 80 #define __APP_PLL_312_RESET_TIMER(_v) ((_v) << __APP_PLL_312_RESET_TIMER_SH) 81 #define __APP_PLL_312_LOGIC_SOFT_RESET 0x00010000 82 #define __APP_PLL_312_CNTLMT0_1_MK 0x0000c000 83 #define __APP_PLL_312_CNTLMT0_1_SH 14 84 #define __APP_PLL_312_CNTLMT0_1(_v) ((_v) << __APP_PLL_312_CNTLMT0_1_SH) 85 #define __APP_PLL_312_JITLMT0_1_MK 0x00003000 86 #define __APP_PLL_312_JITLMT0_1_SH 12 87 #define __APP_PLL_312_JITLMT0_1(_v) ((_v) << __APP_PLL_312_JITLMT0_1_SH) 88 #define __APP_PLL_312_HREF 0x00000800 89 #define __APP_PLL_312_HDIV 0x00000400 90 #define __APP_PLL_312_P0_1_MK 0x00000300 91 #define __APP_PLL_312_P0_1_SH 8 92 #define __APP_PLL_312_P0_1(_v) ((_v) << __APP_PLL_312_P0_1_SH) 93 #define __APP_PLL_312_Z0_2_MK 0x000000e0 94 #define __APP_PLL_312_Z0_2_SH 5 95 #define __APP_PLL_312_Z0_2(_v) ((_v) << __APP_PLL_312_Z0_2_SH) 96 #define __APP_PLL_312_RSEL200500 0x00000010 97 #define __APP_PLL_312_ENARST 0x00000008 98 #define __APP_PLL_312_BYPASS 0x00000004 99 #define __APP_PLL_312_LRESETN 0x00000002 100 #define __APP_PLL_312_ENABLE 0x00000001 101 #define MBIST_CTL_REG 0x00014220 102 #define __EDRAM_BISTR_START 0x00000004 103 #define __MBIST_RESET 0x00000002 104 #define __MBIST_START 0x00000001 105 #define MBIST_STAT_REG 0x00014224 106 #define __EDRAM_BISTR_STATUS 0x00000008 107 #define __EDRAM_BISTR_DONE 0x00000004 108 #define __MEM_BIT_STATUS 0x00000002 109 #define __MBIST_DONE 0x00000001 110 #define HOST_SEM0_REG 0x00014230 111 #define __HOST_SEMAPHORE 0x00000001 112 #define HOST_SEM1_REG 0x00014234 113 #define HOST_SEM2_REG 0x00014238 114 #define HOST_SEM3_REG 0x0001423c 115 #define HOST_SEM0_INFO_REG 0x00014240 116 #define HOST_SEM1_INFO_REG 0x00014244 117 #define HOST_SEM2_INFO_REG 0x00014248 118 #define HOST_SEM3_INFO_REG 0x0001424c 119 #define ETH_MAC_SER_REG 0x00014288 120 #define __APP_EMS_CKBUFAMPIN 0x00000020 121 #define __APP_EMS_REFCLKSEL 0x00000010 122 #define __APP_EMS_CMLCKSEL 0x00000008 123 #define __APP_EMS_REFCKBUFEN2 0x00000004 124 #define __APP_EMS_REFCKBUFEN1 0x00000002 125 #define __APP_EMS_CHANNEL_SEL 0x00000001 126 #define HOSTFN2_INT_STATUS 0x00014300 127 #define __HOSTFN2_HALT_OCCURRED 0x01000000 128 #define __HOSTFN2_INT_STATUS_LVL_MK 0x00f00000 129 #define __HOSTFN2_INT_STATUS_LVL_SH 20 130 #define __HOSTFN2_INT_STATUS_LVL(_v) ((_v) << __HOSTFN2_INT_STATUS_LVL_SH) 131 #define __HOSTFN2_INT_STATUS_P_MK 0x000f0000 132 #define __HOSTFN2_INT_STATUS_P_SH 16 133 #define __HOSTFN2_INT_STATUS_P(_v) ((_v) << __HOSTFN2_INT_STATUS_P_SH) 134 #define __HOSTFN2_INT_STATUS_F 0x0000ffff 135 #define HOSTFN2_INT_MSK 0x00014304 136 #define HOST_PAGE_NUM_FN2 0x00014308 137 #define HOST_MSIX_ERR_INDEX_FN2 0x0001430c 138 #define HOSTFN3_INT_STATUS 0x00014400 139 #define __HALT_OCCURRED 0x01000000 140 #define __HOSTFN3_INT_STATUS_LVL_MK 0x00f00000 141 #define __HOSTFN3_INT_STATUS_LVL_SH 20 142 #define __HOSTFN3_INT_STATUS_LVL(_v) ((_v) << __HOSTFN3_INT_STATUS_LVL_SH) 143 #define __HOSTFN3_INT_STATUS_P_MK 0x000f0000 144 #define __HOSTFN3_INT_STATUS_P_SH 16 145 #define __HOSTFN3_INT_STATUS_P(_v) ((_v) << __HOSTFN3_INT_STATUS_P_SH) 146 #define __HOSTFN3_INT_STATUS_F 0x0000ffff 147 #define HOSTFN3_INT_MSK 0x00014404 148 #define HOST_PAGE_NUM_FN3 0x00014408 149 #define HOST_MSIX_ERR_INDEX_FN3 0x0001440c 150 #define FNC_ID_REG 0x00014600 151 #define __FUNCTION_NUMBER 0x00000007 152 #define FNC_PERS_REG 0x00014604 153 #define __F3_FUNCTION_ACTIVE 0x80000000 154 #define __F3_FUNCTION_MODE 0x40000000 155 #define __F3_PORT_MAP_MK 0x30000000 156 #define __F3_PORT_MAP_SH 28 157 #define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH) 158 #define __F3_VM_MODE 0x08000000 159 #define __F3_INTX_STATUS_MK 0x07000000 160 #define __F3_INTX_STATUS_SH 24 161 #define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH) 162 #define __F2_FUNCTION_ACTIVE 0x00800000 163 #define __F2_FUNCTION_MODE 0x00400000 164 #define __F2_PORT_MAP_MK 0x00300000 165 #define __F2_PORT_MAP_SH 20 166 #define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH) 167 #define __F2_VM_MODE 0x00080000 168 #define __F2_INTX_STATUS_MK 0x00070000 169 #define __F2_INTX_STATUS_SH 16 170 #define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH) 171 #define __F1_FUNCTION_ACTIVE 0x00008000 172 #define __F1_FUNCTION_MODE 0x00004000 173 #define __F1_PORT_MAP_MK 0x00003000 174 #define __F1_PORT_MAP_SH 12 175 #define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH) 176 #define __F1_VM_MODE 0x00000800 177 #define __F1_INTX_STATUS_MK 0x00000700 178 #define __F1_INTX_STATUS_SH 8 179 #define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH) 180 #define __F0_FUNCTION_ACTIVE 0x00000080 181 #define __F0_FUNCTION_MODE 0x00000040 182 #define __F0_PORT_MAP_MK 0x00000030 183 #define __F0_PORT_MAP_SH 4 184 #define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH) 185 #define __F0_VM_MODE 0x00000008 186 #define __F0_INTX_STATUS 0x00000007 187 enum { 188 __F0_INTX_STATUS_MSIX = 0x0, 189 __F0_INTX_STATUS_INTA = 0x1, 190 __F0_INTX_STATUS_INTB = 0x2, 191 __F0_INTX_STATUS_INTC = 0x3, 192 __F0_INTX_STATUS_INTD = 0x4, 193 }; 194 #define OP_MODE 0x0001460c 195 #define __APP_ETH_CLK_LOWSPEED 0x00000004 196 #define __GLOBAL_CORECLK_HALFSPEED 0x00000002 197 #define __GLOBAL_FCOE_MODE 0x00000001 198 #define HOST_SEM4_REG 0x00014610 199 #define HOST_SEM5_REG 0x00014614 200 #define HOST_SEM6_REG 0x00014618 201 #define HOST_SEM7_REG 0x0001461c 202 #define HOST_SEM4_INFO_REG 0x00014620 203 #define HOST_SEM5_INFO_REG 0x00014624 204 #define HOST_SEM6_INFO_REG 0x00014628 205 #define HOST_SEM7_INFO_REG 0x0001462c 206 #define HOSTFN0_LPU0_MBOX0_CMD_STAT 0x00019000 207 #define __HOSTFN0_LPU0_MBOX0_INFO_MK 0xfffffffe 208 #define __HOSTFN0_LPU0_MBOX0_INFO_SH 1 209 #define __HOSTFN0_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU0_MBOX0_INFO_SH) 210 #define __HOSTFN0_LPU0_MBOX0_CMD_STATUS 0x00000001 211 #define HOSTFN0_LPU1_MBOX0_CMD_STAT 0x00019004 212 #define __HOSTFN0_LPU1_MBOX0_INFO_MK 0xfffffffe 213 #define __HOSTFN0_LPU1_MBOX0_INFO_SH 1 214 #define __HOSTFN0_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU1_MBOX0_INFO_SH) 215 #define __HOSTFN0_LPU1_MBOX0_CMD_STATUS 0x00000001 216 #define LPU0_HOSTFN0_MBOX0_CMD_STAT 0x00019008 217 #define __LPU0_HOSTFN0_MBOX0_INFO_MK 0xfffffffe 218 #define __LPU0_HOSTFN0_MBOX0_INFO_SH 1 219 #define __LPU0_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN0_MBOX0_INFO_SH) 220 #define __LPU0_HOSTFN0_MBOX0_CMD_STATUS 0x00000001 221 #define LPU1_HOSTFN0_MBOX0_CMD_STAT 0x0001900c 222 #define __LPU1_HOSTFN0_MBOX0_INFO_MK 0xfffffffe 223 #define __LPU1_HOSTFN0_MBOX0_INFO_SH 1 224 #define __LPU1_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN0_MBOX0_INFO_SH) 225 #define __LPU1_HOSTFN0_MBOX0_CMD_STATUS 0x00000001 226 #define HOSTFN1_LPU0_MBOX0_CMD_STAT 0x00019010 227 #define __HOSTFN1_LPU0_MBOX0_INFO_MK 0xfffffffe 228 #define __HOSTFN1_LPU0_MBOX0_INFO_SH 1 229 #define __HOSTFN1_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU0_MBOX0_INFO_SH) 230 #define __HOSTFN1_LPU0_MBOX0_CMD_STATUS 0x00000001 231 #define HOSTFN1_LPU1_MBOX0_CMD_STAT 0x00019014 232 #define __HOSTFN1_LPU1_MBOX0_INFO_MK 0xfffffffe 233 #define __HOSTFN1_LPU1_MBOX0_INFO_SH 1 234 #define __HOSTFN1_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU1_MBOX0_INFO_SH) 235 #define __HOSTFN1_LPU1_MBOX0_CMD_STATUS 0x00000001 236 #define LPU0_HOSTFN1_MBOX0_CMD_STAT 0x00019018 237 #define __LPU0_HOSTFN1_MBOX0_INFO_MK 0xfffffffe 238 #define __LPU0_HOSTFN1_MBOX0_INFO_SH 1 239 #define __LPU0_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN1_MBOX0_INFO_SH) 240 #define __LPU0_HOSTFN1_MBOX0_CMD_STATUS 0x00000001 241 #define LPU1_HOSTFN1_MBOX0_CMD_STAT 0x0001901c 242 #define __LPU1_HOSTFN1_MBOX0_INFO_MK 0xfffffffe 243 #define __LPU1_HOSTFN1_MBOX0_INFO_SH 1 244 #define __LPU1_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN1_MBOX0_INFO_SH) 245 #define __LPU1_HOSTFN1_MBOX0_CMD_STATUS 0x00000001 246 #define HOSTFN2_LPU0_MBOX0_CMD_STAT 0x00019150 247 #define __HOSTFN2_LPU0_MBOX0_INFO_MK 0xfffffffe 248 #define __HOSTFN2_LPU0_MBOX0_INFO_SH 1 249 #define __HOSTFN2_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU0_MBOX0_INFO_SH) 250 #define __HOSTFN2_LPU0_MBOX0_CMD_STATUS 0x00000001 251 #define HOSTFN2_LPU1_MBOX0_CMD_STAT 0x00019154 252 #define __HOSTFN2_LPU1_MBOX0_INFO_MK 0xfffffffe 253 #define __HOSTFN2_LPU1_MBOX0_INFO_SH 1 254 #define __HOSTFN2_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU1_MBOX0_INFO_SH) 255 #define __HOSTFN2_LPU1_MBOX0BOX0_CMD_STATUS 0x00000001 256 #define LPU0_HOSTFN2_MBOX0_CMD_STAT 0x00019158 257 #define __LPU0_HOSTFN2_MBOX0_INFO_MK 0xfffffffe 258 #define __LPU0_HOSTFN2_MBOX0_INFO_SH 1 259 #define __LPU0_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN2_MBOX0_INFO_SH) 260 #define __LPU0_HOSTFN2_MBOX0_CMD_STATUS 0x00000001 261 #define LPU1_HOSTFN2_MBOX0_CMD_STAT 0x0001915c 262 #define __LPU1_HOSTFN2_MBOX0_INFO_MK 0xfffffffe 263 #define __LPU1_HOSTFN2_MBOX0_INFO_SH 1 264 #define __LPU1_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN2_MBOX0_INFO_SH) 265 #define __LPU1_HOSTFN2_MBOX0_CMD_STATUS 0x00000001 266 #define HOSTFN3_LPU0_MBOX0_CMD_STAT 0x00019160 267 #define __HOSTFN3_LPU0_MBOX0_INFO_MK 0xfffffffe 268 #define __HOSTFN3_LPU0_MBOX0_INFO_SH 1 269 #define __HOSTFN3_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU0_MBOX0_INFO_SH) 270 #define __HOSTFN3_LPU0_MBOX0_CMD_STATUS 0x00000001 271 #define HOSTFN3_LPU1_MBOX0_CMD_STAT 0x00019164 272 #define __HOSTFN3_LPU1_MBOX0_INFO_MK 0xfffffffe 273 #define __HOSTFN3_LPU1_MBOX0_INFO_SH 1 274 #define __HOSTFN3_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU1_MBOX0_INFO_SH) 275 #define __HOSTFN3_LPU1_MBOX0_CMD_STATUS 0x00000001 276 #define LPU0_HOSTFN3_MBOX0_CMD_STAT 0x00019168 277 #define __LPU0_HOSTFN3_MBOX0_INFO_MK 0xfffffffe 278 #define __LPU0_HOSTFN3_MBOX0_INFO_SH 1 279 #define __LPU0_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN3_MBOX0_INFO_SH) 280 #define __LPU0_HOSTFN3_MBOX0_CMD_STATUS 0x00000001 281 #define LPU1_HOSTFN3_MBOX0_CMD_STAT 0x0001916c 282 #define __LPU1_HOSTFN3_MBOX0_INFO_MK 0xfffffffe 283 #define __LPU1_HOSTFN3_MBOX0_INFO_SH 1 284 #define __LPU1_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN3_MBOX0_INFO_SH) 285 #define __LPU1_HOSTFN3_MBOX0_CMD_STATUS 0x00000001 286 #define FW_INIT_HALT_P0 0x000191ac 287 #define __FW_INIT_HALT_P 0x00000001 288 #define FW_INIT_HALT_P1 0x000191bc 289 #define CPE_PI_PTR_Q0 0x00038000 290 #define __CPE_PI_UNUSED_MK 0xffff0000 291 #define __CPE_PI_UNUSED_SH 16 292 #define __CPE_PI_UNUSED(_v) ((_v) << __CPE_PI_UNUSED_SH) 293 #define __CPE_PI_PTR 0x0000ffff 294 #define CPE_PI_PTR_Q1 0x00038040 295 #define CPE_CI_PTR_Q0 0x00038004 296 #define __CPE_CI_UNUSED_MK 0xffff0000 297 #define __CPE_CI_UNUSED_SH 16 298 #define __CPE_CI_UNUSED(_v) ((_v) << __CPE_CI_UNUSED_SH) 299 #define __CPE_CI_PTR 0x0000ffff 300 #define CPE_CI_PTR_Q1 0x00038044 301 #define CPE_DEPTH_Q0 0x00038008 302 #define __CPE_DEPTH_UNUSED_MK 0xf8000000 303 #define __CPE_DEPTH_UNUSED_SH 27 304 #define __CPE_DEPTH_UNUSED(_v) ((_v) << __CPE_DEPTH_UNUSED_SH) 305 #define __CPE_MSIX_VEC_INDEX_MK 0x07ff0000 306 #define __CPE_MSIX_VEC_INDEX_SH 16 307 #define __CPE_MSIX_VEC_INDEX(_v) ((_v) << __CPE_MSIX_VEC_INDEX_SH) 308 #define __CPE_DEPTH 0x0000ffff 309 #define CPE_DEPTH_Q1 0x00038048 310 #define CPE_QCTRL_Q0 0x0003800c 311 #define __CPE_CTRL_UNUSED30_MK 0xfc000000 312 #define __CPE_CTRL_UNUSED30_SH 26 313 #define __CPE_CTRL_UNUSED30(_v) ((_v) << __CPE_CTRL_UNUSED30_SH) 314 #define __CPE_FUNC_INT_CTRL_MK 0x03000000 315 #define __CPE_FUNC_INT_CTRL_SH 24 316 #define __CPE_FUNC_INT_CTRL(_v) ((_v) << __CPE_FUNC_INT_CTRL_SH) 317 enum { 318 __CPE_FUNC_INT_CTRL_DISABLE = 0x0, 319 __CPE_FUNC_INT_CTRL_F2NF = 0x1, 320 __CPE_FUNC_INT_CTRL_3QUART = 0x2, 321 __CPE_FUNC_INT_CTRL_HALF = 0x3, 322 }; 323 #define __CPE_CTRL_UNUSED20_MK 0x00f00000 324 #define __CPE_CTRL_UNUSED20_SH 20 325 #define __CPE_CTRL_UNUSED20(_v) ((_v) << __CPE_CTRL_UNUSED20_SH) 326 #define __CPE_SCI_TH_MK 0x000f0000 327 #define __CPE_SCI_TH_SH 16 328 #define __CPE_SCI_TH(_v) ((_v) << __CPE_SCI_TH_SH) 329 #define __CPE_CTRL_UNUSED10_MK 0x0000c000 330 #define __CPE_CTRL_UNUSED10_SH 14 331 #define __CPE_CTRL_UNUSED10(_v) ((_v) << __CPE_CTRL_UNUSED10_SH) 332 #define __CPE_ACK_PENDING 0x00002000 333 #define __CPE_CTRL_UNUSED40_MK 0x00001c00 334 #define __CPE_CTRL_UNUSED40_SH 10 335 #define __CPE_CTRL_UNUSED40(_v) ((_v) << __CPE_CTRL_UNUSED40_SH) 336 #define __CPE_PCIEID_MK 0x00000300 337 #define __CPE_PCIEID_SH 8 338 #define __CPE_PCIEID(_v) ((_v) << __CPE_PCIEID_SH) 339 #define __CPE_CTRL_UNUSED00_MK 0x000000fe 340 #define __CPE_CTRL_UNUSED00_SH 1 341 #define __CPE_CTRL_UNUSED00(_v) ((_v) << __CPE_CTRL_UNUSED00_SH) 342 #define __CPE_ESIZE 0x00000001 343 #define CPE_QCTRL_Q1 0x0003804c 344 #define __CPE_CTRL_UNUSED31_MK 0xfc000000 345 #define __CPE_CTRL_UNUSED31_SH 26 346 #define __CPE_CTRL_UNUSED31(_v) ((_v) << __CPE_CTRL_UNUSED31_SH) 347 #define __CPE_CTRL_UNUSED21_MK 0x00f00000 348 #define __CPE_CTRL_UNUSED21_SH 20 349 #define __CPE_CTRL_UNUSED21(_v) ((_v) << __CPE_CTRL_UNUSED21_SH) 350 #define __CPE_CTRL_UNUSED11_MK 0x0000c000 351 #define __CPE_CTRL_UNUSED11_SH 14 352 #define __CPE_CTRL_UNUSED11(_v) ((_v) << __CPE_CTRL_UNUSED11_SH) 353 #define __CPE_CTRL_UNUSED41_MK 0x00001c00 354 #define __CPE_CTRL_UNUSED41_SH 10 355 #define __CPE_CTRL_UNUSED41(_v) ((_v) << __CPE_CTRL_UNUSED41_SH) 356 #define __CPE_CTRL_UNUSED01_MK 0x000000fe 357 #define __CPE_CTRL_UNUSED01_SH 1 358 #define __CPE_CTRL_UNUSED01(_v) ((_v) << __CPE_CTRL_UNUSED01_SH) 359 #define RME_PI_PTR_Q0 0x00038020 360 #define __LATENCY_TIME_STAMP_MK 0xffff0000 361 #define __LATENCY_TIME_STAMP_SH 16 362 #define __LATENCY_TIME_STAMP(_v) ((_v) << __LATENCY_TIME_STAMP_SH) 363 #define __RME_PI_PTR 0x0000ffff 364 #define RME_PI_PTR_Q1 0x00038060 365 #define RME_CI_PTR_Q0 0x00038024 366 #define __DELAY_TIME_STAMP_MK 0xffff0000 367 #define __DELAY_TIME_STAMP_SH 16 368 #define __DELAY_TIME_STAMP(_v) ((_v) << __DELAY_TIME_STAMP_SH) 369 #define __RME_CI_PTR 0x0000ffff 370 #define RME_CI_PTR_Q1 0x00038064 371 #define RME_DEPTH_Q0 0x00038028 372 #define __RME_DEPTH_UNUSED_MK 0xf8000000 373 #define __RME_DEPTH_UNUSED_SH 27 374 #define __RME_DEPTH_UNUSED(_v) ((_v) << __RME_DEPTH_UNUSED_SH) 375 #define __RME_MSIX_VEC_INDEX_MK 0x07ff0000 376 #define __RME_MSIX_VEC_INDEX_SH 16 377 #define __RME_MSIX_VEC_INDEX(_v) ((_v) << __RME_MSIX_VEC_INDEX_SH) 378 #define __RME_DEPTH 0x0000ffff 379 #define RME_DEPTH_Q1 0x00038068 380 #define RME_QCTRL_Q0 0x0003802c 381 #define __RME_INT_LATENCY_TIMER_MK 0xff000000 382 #define __RME_INT_LATENCY_TIMER_SH 24 383 #define __RME_INT_LATENCY_TIMER(_v) ((_v) << __RME_INT_LATENCY_TIMER_SH) 384 #define __RME_INT_DELAY_TIMER_MK 0x00ff0000 385 #define __RME_INT_DELAY_TIMER_SH 16 386 #define __RME_INT_DELAY_TIMER(_v) ((_v) << __RME_INT_DELAY_TIMER_SH) 387 #define __RME_INT_DELAY_DISABLE 0x00008000 388 #define __RME_DLY_DELAY_DISABLE 0x00004000 389 #define __RME_ACK_PENDING 0x00002000 390 #define __RME_FULL_INTERRUPT_DISABLE 0x00001000 391 #define __RME_CTRL_UNUSED10_MK 0x00000c00 392 #define __RME_CTRL_UNUSED10_SH 10 393 #define __RME_CTRL_UNUSED10(_v) ((_v) << __RME_CTRL_UNUSED10_SH) 394 #define __RME_PCIEID_MK 0x00000300 395 #define __RME_PCIEID_SH 8 396 #define __RME_PCIEID(_v) ((_v) << __RME_PCIEID_SH) 397 #define __RME_CTRL_UNUSED00_MK 0x000000fe 398 #define __RME_CTRL_UNUSED00_SH 1 399 #define __RME_CTRL_UNUSED00(_v) ((_v) << __RME_CTRL_UNUSED00_SH) 400 #define __RME_ESIZE 0x00000001 401 #define RME_QCTRL_Q1 0x0003806c 402 #define __RME_CTRL_UNUSED11_MK 0x00000c00 403 #define __RME_CTRL_UNUSED11_SH 10 404 #define __RME_CTRL_UNUSED11(_v) ((_v) << __RME_CTRL_UNUSED11_SH) 405 #define __RME_CTRL_UNUSED01_MK 0x000000fe 406 #define __RME_CTRL_UNUSED01_SH 1 407 #define __RME_CTRL_UNUSED01(_v) ((_v) << __RME_CTRL_UNUSED01_SH) 408 #define PSS_CTL_REG 0x00018800 409 #define __PSS_I2C_CLK_DIV_MK 0x007f0000 410 #define __PSS_I2C_CLK_DIV_SH 16 411 #define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH) 412 #define __PSS_LMEM_INIT_DONE 0x00001000 413 #define __PSS_LMEM_RESET 0x00000200 414 #define __PSS_LMEM_INIT_EN 0x00000100 415 #define __PSS_LPU1_RESET 0x00000002 416 #define __PSS_LPU0_RESET 0x00000001 417 #define PSS_ERR_STATUS_REG 0x00018810 418 #define __PSS_LPU1_TCM_READ_ERR 0x00200000 419 #define __PSS_LPU0_TCM_READ_ERR 0x00100000 420 #define __PSS_LMEM5_CORR_ERR 0x00080000 421 #define __PSS_LMEM4_CORR_ERR 0x00040000 422 #define __PSS_LMEM3_CORR_ERR 0x00020000 423 #define __PSS_LMEM2_CORR_ERR 0x00010000 424 #define __PSS_LMEM1_CORR_ERR 0x00008000 425 #define __PSS_LMEM0_CORR_ERR 0x00004000 426 #define __PSS_LMEM5_UNCORR_ERR 0x00002000 427 #define __PSS_LMEM4_UNCORR_ERR 0x00001000 428 #define __PSS_LMEM3_UNCORR_ERR 0x00000800 429 #define __PSS_LMEM2_UNCORR_ERR 0x00000400 430 #define __PSS_LMEM1_UNCORR_ERR 0x00000200 431 #define __PSS_LMEM0_UNCORR_ERR 0x00000100 432 #define __PSS_BAL_PERR 0x00000080 433 #define __PSS_DIP_IF_ERR 0x00000040 434 #define __PSS_IOH_IF_ERR 0x00000020 435 #define __PSS_TDS_IF_ERR 0x00000010 436 #define __PSS_RDS_IF_ERR 0x00000008 437 #define __PSS_SGM_IF_ERR 0x00000004 438 #define __PSS_LPU1_RAM_ERR 0x00000002 439 #define __PSS_LPU0_RAM_ERR 0x00000001 440 #define ERR_SET_REG 0x00018818 441 #define __PSS_ERR_STATUS_SET 0x003fffff 442 #define PMM_1T_RESET_REG_P0 0x0002381c 443 #define __PMM_1T_RESET_P 0x00000001 444 #define PMM_1T_RESET_REG_P1 0x00023c1c 445 #define HQM_QSET0_RXQ_DRBL_P0 0x00038000 446 #define __RXQ0_ADD_VECTORS_P 0x80000000 447 #define __RXQ0_STOP_P 0x40000000 448 #define __RXQ0_PRD_PTR_P 0x0000ffff 449 #define HQM_QSET1_RXQ_DRBL_P0 0x00038080 450 #define __RXQ1_ADD_VECTORS_P 0x80000000 451 #define __RXQ1_STOP_P 0x40000000 452 #define __RXQ1_PRD_PTR_P 0x0000ffff 453 #define HQM_QSET0_RXQ_DRBL_P1 0x0003c000 454 #define HQM_QSET1_RXQ_DRBL_P1 0x0003c080 455 #define HQM_QSET0_TXQ_DRBL_P0 0x00038020 456 #define __TXQ0_ADD_VECTORS_P 0x80000000 457 #define __TXQ0_STOP_P 0x40000000 458 #define __TXQ0_PRD_PTR_P 0x0000ffff 459 #define HQM_QSET1_TXQ_DRBL_P0 0x000380a0 460 #define __TXQ1_ADD_VECTORS_P 0x80000000 461 #define __TXQ1_STOP_P 0x40000000 462 #define __TXQ1_PRD_PTR_P 0x0000ffff 463 #define HQM_QSET0_TXQ_DRBL_P1 0x0003c020 464 #define HQM_QSET1_TXQ_DRBL_P1 0x0003c0a0 465 #define HQM_QSET0_IB_DRBL_1_P0 0x00038040 466 #define __IB1_0_ACK_P 0x80000000 467 #define __IB1_0_DISABLE_P 0x40000000 468 #define __IB1_0_COALESCING_CFG_P_MK 0x00ff0000 469 #define __IB1_0_COALESCING_CFG_P_SH 16 470 #define __IB1_0_COALESCING_CFG_P(_v) ((_v) << __IB1_0_COALESCING_CFG_P_SH) 471 #define __IB1_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff 472 #define HQM_QSET1_IB_DRBL_1_P0 0x000380c0 473 #define __IB1_1_ACK_P 0x80000000 474 #define __IB1_1_DISABLE_P 0x40000000 475 #define __IB1_1_COALESCING_CFG_P_MK 0x00ff0000 476 #define __IB1_1_COALESCING_CFG_P_SH 16 477 #define __IB1_1_COALESCING_CFG_P(_v) ((_v) << __IB1_1_COALESCING_CFG_P_SH) 478 #define __IB1_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff 479 #define HQM_QSET0_IB_DRBL_1_P1 0x0003c040 480 #define HQM_QSET1_IB_DRBL_1_P1 0x0003c0c0 481 #define HQM_QSET0_IB_DRBL_2_P0 0x00038060 482 #define __IB2_0_ACK_P 0x80000000 483 #define __IB2_0_DISABLE_P 0x40000000 484 #define __IB2_0_COALESCING_CFG_P_MK 0x00ff0000 485 #define __IB2_0_COALESCING_CFG_P_SH 16 486 #define __IB2_0_COALESCING_CFG_P(_v) ((_v) << __IB2_0_COALESCING_CFG_P_SH) 487 #define __IB2_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff 488 #define HQM_QSET1_IB_DRBL_2_P0 0x000380e0 489 #define __IB2_1_ACK_P 0x80000000 490 #define __IB2_1_DISABLE_P 0x40000000 491 #define __IB2_1_COALESCING_CFG_P_MK 0x00ff0000 492 #define __IB2_1_COALESCING_CFG_P_SH 16 493 #define __IB2_1_COALESCING_CFG_P(_v) ((_v) << __IB2_1_COALESCING_CFG_P_SH) 494 #define __IB2_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff 495 #define HQM_QSET0_IB_DRBL_2_P1 0x0003c060 496 #define HQM_QSET1_IB_DRBL_2_P1 0x0003c0e0 497 498 499 /* 500 * These definitions are either in error/missing in spec. Its auto-generated 501 * from hard coded values in regparse.pl. 502 */ 503 #define __EMPHPOST_AT_4G_MK_FIX 0x0000001c 504 #define __EMPHPOST_AT_4G_SH_FIX 0x00000002 505 #define __EMPHPRE_AT_4G_FIX 0x00000003 506 #define __SFP_TXRATE_EN_FIX 0x00000100 507 #define __SFP_RXRATE_EN_FIX 0x00000080 508 509 510 /* 511 * These register definitions are auto-generated from hard coded values 512 * in regparse.pl. 513 */ 514 515 516 /* 517 * These register mapping definitions are auto-generated from mapping tables 518 * in regparse.pl. 519 */ 520 #define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG 521 #define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG 522 #define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG 523 #define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG 524 #define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG 525 #define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG 526 527 #define CPE_DEPTH_Q(__n) \ 528 (CPE_DEPTH_Q0 + (__n) * (CPE_DEPTH_Q1 - CPE_DEPTH_Q0)) 529 #define CPE_QCTRL_Q(__n) \ 530 (CPE_QCTRL_Q0 + (__n) * (CPE_QCTRL_Q1 - CPE_QCTRL_Q0)) 531 #define CPE_PI_PTR_Q(__n) \ 532 (CPE_PI_PTR_Q0 + (__n) * (CPE_PI_PTR_Q1 - CPE_PI_PTR_Q0)) 533 #define CPE_CI_PTR_Q(__n) \ 534 (CPE_CI_PTR_Q0 + (__n) * (CPE_CI_PTR_Q1 - CPE_CI_PTR_Q0)) 535 #define RME_DEPTH_Q(__n) \ 536 (RME_DEPTH_Q0 + (__n) * (RME_DEPTH_Q1 - RME_DEPTH_Q0)) 537 #define RME_QCTRL_Q(__n) \ 538 (RME_QCTRL_Q0 + (__n) * (RME_QCTRL_Q1 - RME_QCTRL_Q0)) 539 #define RME_PI_PTR_Q(__n) \ 540 (RME_PI_PTR_Q0 + (__n) * (RME_PI_PTR_Q1 - RME_PI_PTR_Q0)) 541 #define RME_CI_PTR_Q(__n) \ 542 (RME_CI_PTR_Q0 + (__n) * (RME_CI_PTR_Q1 - RME_CI_PTR_Q0)) 543 #define HQM_QSET_RXQ_DRBL_P0(__n) \ 544 (HQM_QSET0_RXQ_DRBL_P0 + (__n) * \ 545 (HQM_QSET1_RXQ_DRBL_P0 - HQM_QSET0_RXQ_DRBL_P0)) 546 #define HQM_QSET_TXQ_DRBL_P0(__n) \ 547 (HQM_QSET0_TXQ_DRBL_P0 + (__n) * \ 548 (HQM_QSET1_TXQ_DRBL_P0 - HQM_QSET0_TXQ_DRBL_P0)) 549 #define HQM_QSET_IB_DRBL_1_P0(__n) \ 550 (HQM_QSET0_IB_DRBL_1_P0 + (__n) * \ 551 (HQM_QSET1_IB_DRBL_1_P0 - HQM_QSET0_IB_DRBL_1_P0)) 552 #define HQM_QSET_IB_DRBL_2_P0(__n) \ 553 (HQM_QSET0_IB_DRBL_2_P0 + (__n) * \ 554 (HQM_QSET1_IB_DRBL_2_P0 - HQM_QSET0_IB_DRBL_2_P0)) 555 #define HQM_QSET_RXQ_DRBL_P1(__n) \ 556 (HQM_QSET0_RXQ_DRBL_P1 + (__n) * \ 557 (HQM_QSET1_RXQ_DRBL_P1 - HQM_QSET0_RXQ_DRBL_P1)) 558 #define HQM_QSET_TXQ_DRBL_P1(__n) \ 559 (HQM_QSET0_TXQ_DRBL_P1 + (__n) * \ 560 (HQM_QSET1_TXQ_DRBL_P1 - HQM_QSET0_TXQ_DRBL_P1)) 561 #define HQM_QSET_IB_DRBL_1_P1(__n) \ 562 (HQM_QSET0_IB_DRBL_1_P1 + (__n) * \ 563 (HQM_QSET1_IB_DRBL_1_P1 - HQM_QSET0_IB_DRBL_1_P1)) 564 #define HQM_QSET_IB_DRBL_2_P1(__n) \ 565 (HQM_QSET0_IB_DRBL_2_P1 + (__n) * \ 566 (HQM_QSET1_IB_DRBL_2_P1 - HQM_QSET0_IB_DRBL_2_P1)) 567 568 #define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) 569 #define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q)) 570 #define CPE_Q_MASK(__q) ((__q) & 0x3) 571 #define RME_Q_MASK(__q) ((__q) & 0x3) 572 573 574 /* 575 * PCI MSI-X vector defines 576 */ 577 enum { 578 BFA_MSIX_CPE_Q0 = 0, 579 BFA_MSIX_CPE_Q1 = 1, 580 BFA_MSIX_CPE_Q2 = 2, 581 BFA_MSIX_CPE_Q3 = 3, 582 BFA_MSIX_RME_Q0 = 4, 583 BFA_MSIX_RME_Q1 = 5, 584 BFA_MSIX_RME_Q2 = 6, 585 BFA_MSIX_RME_Q3 = 7, 586 BFA_MSIX_LPU_ERR = 8, 587 BFA_MSIX_CT_MAX = 9, 588 }; 589 590 /* 591 * And corresponding host interrupt status bit field defines 592 */ 593 #define __HFN_INT_CPE_Q0 0x00000001U 594 #define __HFN_INT_CPE_Q1 0x00000002U 595 #define __HFN_INT_CPE_Q2 0x00000004U 596 #define __HFN_INT_CPE_Q3 0x00000008U 597 #define __HFN_INT_CPE_Q4 0x00000010U 598 #define __HFN_INT_CPE_Q5 0x00000020U 599 #define __HFN_INT_CPE_Q6 0x00000040U 600 #define __HFN_INT_CPE_Q7 0x00000080U 601 #define __HFN_INT_RME_Q0 0x00000100U 602 #define __HFN_INT_RME_Q1 0x00000200U 603 #define __HFN_INT_RME_Q2 0x00000400U 604 #define __HFN_INT_RME_Q3 0x00000800U 605 #define __HFN_INT_RME_Q4 0x00001000U 606 #define __HFN_INT_RME_Q5 0x00002000U 607 #define __HFN_INT_RME_Q6 0x00004000U 608 #define __HFN_INT_RME_Q7 0x00008000U 609 #define __HFN_INT_ERR_EMC 0x00010000U 610 #define __HFN_INT_ERR_LPU0 0x00020000U 611 #define __HFN_INT_ERR_LPU1 0x00040000U 612 #define __HFN_INT_ERR_PSS 0x00080000U 613 #define __HFN_INT_MBOX_LPU0 0x00100000U 614 #define __HFN_INT_MBOX_LPU1 0x00200000U 615 #define __HFN_INT_MBOX1_LPU0 0x00400000U 616 #define __HFN_INT_MBOX1_LPU1 0x00800000U 617 #define __HFN_INT_LL_HALT 0x01000000U 618 #define __HFN_INT_CPE_MASK 0x000000ffU 619 #define __HFN_INT_RME_MASK 0x0000ff00U 620 621 622 /* 623 * catapult memory map. 624 */ 625 #define LL_PGN_HQM0 0x0096 626 #define LL_PGN_HQM1 0x0097 627 #define PSS_SMEM_PAGE_START 0x8000 628 #define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15)) 629 #define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff) 630 631 /* 632 * End of catapult memory map 633 */ 634 635 636 #endif /* __BFI_CTREG_H__ */ 637