1 /*
2 * SuperH IrDA Driver
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on bfin_sir.c
8 * Copyright 2006-2009 Analog Devices Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 #include <net/irda/wrapper.h>
19 #include <net/irda/irda_device.h>
20 #include <asm/clock.h>
21
22 #define DRIVER_NAME "sh_sir"
23
24 #define RX_PHASE (1 << 0)
25 #define TX_PHASE (1 << 1)
26 #define TX_COMP_PHASE (1 << 2) /* tx complete */
27 #define NONE_PHASE (1 << 31)
28
29 #define IRIF_RINTCLR 0x0016 /* DMA rx interrupt source clear */
30 #define IRIF_TINTCLR 0x0018 /* DMA tx interrupt source clear */
31 #define IRIF_SIR0 0x0020 /* IrDA-SIR10 control */
32 #define IRIF_SIR1 0x0022 /* IrDA-SIR10 baudrate error correction */
33 #define IRIF_SIR2 0x0024 /* IrDA-SIR10 baudrate count */
34 #define IRIF_SIR3 0x0026 /* IrDA-SIR10 status */
35 #define IRIF_SIR_FRM 0x0028 /* Hardware frame processing set */
36 #define IRIF_SIR_EOF 0x002A /* EOF value */
37 #define IRIF_SIR_FLG 0x002C /* Flag clear */
38 #define IRIF_UART_STS2 0x002E /* UART status 2 */
39 #define IRIF_UART0 0x0030 /* UART control */
40 #define IRIF_UART1 0x0032 /* UART status */
41 #define IRIF_UART2 0x0034 /* UART mode */
42 #define IRIF_UART3 0x0036 /* UART transmit data */
43 #define IRIF_UART4 0x0038 /* UART receive data */
44 #define IRIF_UART5 0x003A /* UART interrupt mask */
45 #define IRIF_UART6 0x003C /* UART baud rate error correction */
46 #define IRIF_UART7 0x003E /* UART baud rate count set */
47 #define IRIF_CRC0 0x0040 /* CRC engine control */
48 #define IRIF_CRC1 0x0042 /* CRC engine input data */
49 #define IRIF_CRC2 0x0044 /* CRC engine calculation */
50 #define IRIF_CRC3 0x0046 /* CRC engine output data 1 */
51 #define IRIF_CRC4 0x0048 /* CRC engine output data 2 */
52
53 /* IRIF_SIR0 */
54 #define IRTPW (1 << 1) /* transmit pulse width select */
55 #define IRERRC (1 << 0) /* Clear receive pulse width error */
56
57 /* IRIF_SIR3 */
58 #define IRERR (1 << 0) /* received pulse width Error */
59
60 /* IRIF_SIR_FRM */
61 #define EOFD (1 << 9) /* EOF detection flag */
62 #define FRER (1 << 8) /* Frame Error bit */
63 #define FRP (1 << 0) /* Frame processing set */
64
65 /* IRIF_UART_STS2 */
66 #define IRSME (1 << 6) /* Receive Sum Error flag */
67 #define IROVE (1 << 5) /* Receive Overrun Error flag */
68 #define IRFRE (1 << 4) /* Receive Framing Error flag */
69 #define IRPRE (1 << 3) /* Receive Parity Error flag */
70
71 /* IRIF_UART0_*/
72 #define TBEC (1 << 2) /* Transmit Data Clear */
73 #define RIE (1 << 1) /* Receive Enable */
74 #define TIE (1 << 0) /* Transmit Enable */
75
76 /* IRIF_UART1 */
77 #define URSME (1 << 6) /* Receive Sum Error Flag */
78 #define UROVE (1 << 5) /* Receive Overrun Error Flag */
79 #define URFRE (1 << 4) /* Receive Framing Error Flag */
80 #define URPRE (1 << 3) /* Receive Parity Error Flag */
81 #define RBF (1 << 2) /* Receive Buffer Full Flag */
82 #define TSBE (1 << 1) /* Transmit Shift Buffer Empty Flag */
83 #define TBE (1 << 0) /* Transmit Buffer Empty flag */
84 #define TBCOMP (TSBE | TBE)
85
86 /* IRIF_UART5 */
87 #define RSEIM (1 << 6) /* Receive Sum Error Flag IRQ Mask */
88 #define RBFIM (1 << 2) /* Receive Buffer Full Flag IRQ Mask */
89 #define TSBEIM (1 << 1) /* Transmit Shift Buffer Empty Flag IRQ Mask */
90 #define TBEIM (1 << 0) /* Transmit Buffer Empty Flag IRQ Mask */
91 #define RX_MASK (RSEIM | RBFIM)
92
93 /* IRIF_CRC0 */
94 #define CRC_RST (1 << 15) /* CRC Engine Reset */
95 #define CRC_CT_MASK 0x0FFF
96
97 /************************************************************************
98
99
100 structure
101
102
103 ************************************************************************/
104 struct sh_sir_self {
105 void __iomem *membase;
106 unsigned int irq;
107 struct clk *clk;
108
109 struct net_device *ndev;
110
111 struct irlap_cb *irlap;
112 struct qos_info qos;
113
114 iobuff_t tx_buff;
115 iobuff_t rx_buff;
116 };
117
118 /************************************************************************
119
120
121 common function
122
123
124 ************************************************************************/
sh_sir_write(struct sh_sir_self * self,u32 offset,u16 data)125 static void sh_sir_write(struct sh_sir_self *self, u32 offset, u16 data)
126 {
127 iowrite16(data, self->membase + offset);
128 }
129
sh_sir_read(struct sh_sir_self * self,u32 offset)130 static u16 sh_sir_read(struct sh_sir_self *self, u32 offset)
131 {
132 return ioread16(self->membase + offset);
133 }
134
sh_sir_update_bits(struct sh_sir_self * self,u32 offset,u16 mask,u16 data)135 static void sh_sir_update_bits(struct sh_sir_self *self, u32 offset,
136 u16 mask, u16 data)
137 {
138 u16 old, new;
139
140 old = sh_sir_read(self, offset);
141 new = (old & ~mask) | data;
142 if (old != new)
143 sh_sir_write(self, offset, new);
144 }
145
146 /************************************************************************
147
148
149 CRC function
150
151
152 ************************************************************************/
sh_sir_crc_reset(struct sh_sir_self * self)153 static void sh_sir_crc_reset(struct sh_sir_self *self)
154 {
155 sh_sir_write(self, IRIF_CRC0, CRC_RST);
156 }
157
sh_sir_crc_add(struct sh_sir_self * self,u8 data)158 static void sh_sir_crc_add(struct sh_sir_self *self, u8 data)
159 {
160 sh_sir_write(self, IRIF_CRC1, (u16)data);
161 }
162
sh_sir_crc_cnt(struct sh_sir_self * self)163 static u16 sh_sir_crc_cnt(struct sh_sir_self *self)
164 {
165 return CRC_CT_MASK & sh_sir_read(self, IRIF_CRC0);
166 }
167
sh_sir_crc_out(struct sh_sir_self * self)168 static u16 sh_sir_crc_out(struct sh_sir_self *self)
169 {
170 return sh_sir_read(self, IRIF_CRC4);
171 }
172
sh_sir_crc_init(struct sh_sir_self * self)173 static int sh_sir_crc_init(struct sh_sir_self *self)
174 {
175 struct device *dev = &self->ndev->dev;
176 int ret = -EIO;
177 u16 val;
178
179 sh_sir_crc_reset(self);
180
181 sh_sir_crc_add(self, 0xCC);
182 sh_sir_crc_add(self, 0xF5);
183 sh_sir_crc_add(self, 0xF1);
184 sh_sir_crc_add(self, 0xA7);
185
186 val = sh_sir_crc_cnt(self);
187 if (4 != val) {
188 dev_err(dev, "CRC count error %x\n", val);
189 goto crc_init_out;
190 }
191
192 val = sh_sir_crc_out(self);
193 if (0x51DF != val) {
194 dev_err(dev, "CRC result error%x\n", val);
195 goto crc_init_out;
196 }
197
198 ret = 0;
199
200 crc_init_out:
201
202 sh_sir_crc_reset(self);
203 return ret;
204 }
205
206 /************************************************************************
207
208
209 baud rate functions
210
211
212 ************************************************************************/
213 #define SCLK_BASE 1843200 /* 1.8432MHz */
214
sh_sir_find_sclk(struct clk * irda_clk)215 static u32 sh_sir_find_sclk(struct clk *irda_clk)
216 {
217 struct cpufreq_frequency_table *freq_table = irda_clk->freq_table;
218 struct clk *pclk = clk_get(NULL, "peripheral_clk");
219 u32 limit, min = 0xffffffff, tmp;
220 int i, index = 0;
221
222 limit = clk_get_rate(pclk);
223 clk_put(pclk);
224
225 /* IrDA can not set over peripheral_clk */
226 for (i = 0;
227 freq_table[i].frequency != CPUFREQ_TABLE_END;
228 i++) {
229 u32 freq = freq_table[i].frequency;
230
231 if (freq == CPUFREQ_ENTRY_INVALID)
232 continue;
233
234 /* IrDA should not over peripheral_clk */
235 if (freq > limit)
236 continue;
237
238 tmp = freq % SCLK_BASE;
239 if (tmp < min) {
240 min = tmp;
241 index = i;
242 }
243 }
244
245 return freq_table[index].frequency;
246 }
247
248 #define ERR_ROUNDING(a) ((a + 5000) / 10000)
sh_sir_set_baudrate(struct sh_sir_self * self,u32 baudrate)249 static int sh_sir_set_baudrate(struct sh_sir_self *self, u32 baudrate)
250 {
251 struct clk *clk;
252 struct device *dev = &self->ndev->dev;
253 u32 rate;
254 u16 uabca, uabc;
255 u16 irbca, irbc;
256 u32 min, rerr, tmp;
257 int i;
258
259 /* Baud Rate Error Correction x 10000 */
260 u32 rate_err_array[] = {
261 0, 625, 1250, 1875,
262 2500, 3125, 3750, 4375,
263 5000, 5625, 6250, 6875,
264 7500, 8125, 8750, 9375,
265 };
266
267 /*
268 * FIXME
269 *
270 * it support 9600 only now
271 */
272 switch (baudrate) {
273 case 9600:
274 break;
275 default:
276 dev_err(dev, "un-supported baudrate %d\n", baudrate);
277 return -EIO;
278 }
279
280 clk = clk_get(NULL, "irda_clk");
281 if (!clk) {
282 dev_err(dev, "can not get irda_clk\n");
283 return -EIO;
284 }
285
286 clk_set_rate(clk, sh_sir_find_sclk(clk));
287 rate = clk_get_rate(clk);
288 clk_put(clk);
289
290 dev_dbg(dev, "selected sclk = %d\n", rate);
291
292 /*
293 * CALCULATION
294 *
295 * 1843200 = system rate / (irbca + (irbc + 1))
296 */
297
298 irbc = rate / SCLK_BASE;
299
300 tmp = rate - (SCLK_BASE * irbc);
301 tmp *= 10000;
302
303 rerr = tmp / SCLK_BASE;
304
305 min = 0xffffffff;
306 irbca = 0;
307 for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) {
308 tmp = abs(rate_err_array[i] - rerr);
309 if (min > tmp) {
310 min = tmp;
311 irbca = i;
312 }
313 }
314
315 tmp = rate / (irbc + ERR_ROUNDING(rate_err_array[irbca]));
316 if ((SCLK_BASE / 100) < abs(tmp - SCLK_BASE))
317 dev_warn(dev, "IrDA freq error margin over %d\n", tmp);
318
319 dev_dbg(dev, "target = %d, result = %d, infrared = %d.%d\n",
320 SCLK_BASE, tmp, irbc, rate_err_array[irbca]);
321
322 irbca = (irbca & 0xF) << 4;
323 irbc = (irbc - 1) & 0xF;
324
325 if (!irbc) {
326 dev_err(dev, "sh_sir can not set 0 in IRIF_SIR2\n");
327 return -EIO;
328 }
329
330 sh_sir_write(self, IRIF_SIR0, IRTPW | IRERRC);
331 sh_sir_write(self, IRIF_SIR1, irbca);
332 sh_sir_write(self, IRIF_SIR2, irbc);
333
334 /*
335 * CALCULATION
336 *
337 * BaudRate[bps] = system rate / (uabca + (uabc + 1) x 16)
338 */
339
340 uabc = rate / baudrate;
341 uabc = (uabc / 16) - 1;
342 uabc = (uabc + 1) * 16;
343
344 tmp = rate - (uabc * baudrate);
345 tmp *= 10000;
346
347 rerr = tmp / baudrate;
348
349 min = 0xffffffff;
350 uabca = 0;
351 for (i = 0; i < ARRAY_SIZE(rate_err_array); i++) {
352 tmp = abs(rate_err_array[i] - rerr);
353 if (min > tmp) {
354 min = tmp;
355 uabca = i;
356 }
357 }
358
359 tmp = rate / (uabc + ERR_ROUNDING(rate_err_array[uabca]));
360 if ((baudrate / 100) < abs(tmp - baudrate))
361 dev_warn(dev, "UART freq error margin over %d\n", tmp);
362
363 dev_dbg(dev, "target = %d, result = %d, uart = %d.%d\n",
364 baudrate, tmp,
365 uabc, rate_err_array[uabca]);
366
367 uabca = (uabca & 0xF) << 4;
368 uabc = (uabc / 16) - 1;
369
370 sh_sir_write(self, IRIF_UART6, uabca);
371 sh_sir_write(self, IRIF_UART7, uabc);
372
373 return 0;
374 }
375
376 /************************************************************************
377
378
379 iobuf function
380
381
382 ************************************************************************/
__sh_sir_init_iobuf(iobuff_t * io,int size)383 static int __sh_sir_init_iobuf(iobuff_t *io, int size)
384 {
385 io->head = kmalloc(size, GFP_KERNEL);
386 if (!io->head)
387 return -ENOMEM;
388
389 io->truesize = size;
390 io->in_frame = FALSE;
391 io->state = OUTSIDE_FRAME;
392 io->data = io->head;
393
394 return 0;
395 }
396
sh_sir_remove_iobuf(struct sh_sir_self * self)397 static void sh_sir_remove_iobuf(struct sh_sir_self *self)
398 {
399 kfree(self->rx_buff.head);
400 kfree(self->tx_buff.head);
401
402 self->rx_buff.head = NULL;
403 self->tx_buff.head = NULL;
404 }
405
sh_sir_init_iobuf(struct sh_sir_self * self,int rxsize,int txsize)406 static int sh_sir_init_iobuf(struct sh_sir_self *self, int rxsize, int txsize)
407 {
408 int err = -ENOMEM;
409
410 if (self->rx_buff.head ||
411 self->tx_buff.head) {
412 dev_err(&self->ndev->dev, "iobuff has already existed.");
413 return err;
414 }
415
416 err = __sh_sir_init_iobuf(&self->rx_buff, rxsize);
417 if (err)
418 goto iobuf_err;
419
420 err = __sh_sir_init_iobuf(&self->tx_buff, txsize);
421
422 iobuf_err:
423 if (err)
424 sh_sir_remove_iobuf(self);
425
426 return err;
427 }
428
429 /************************************************************************
430
431
432 status function
433
434
435 ************************************************************************/
sh_sir_clear_all_err(struct sh_sir_self * self)436 static void sh_sir_clear_all_err(struct sh_sir_self *self)
437 {
438 /* Clear error flag for receive pulse width */
439 sh_sir_update_bits(self, IRIF_SIR0, IRERRC, IRERRC);
440
441 /* Clear frame / EOF error flag */
442 sh_sir_write(self, IRIF_SIR_FLG, 0xffff);
443
444 /* Clear all status error */
445 sh_sir_write(self, IRIF_UART_STS2, 0);
446 }
447
sh_sir_set_phase(struct sh_sir_self * self,int phase)448 static void sh_sir_set_phase(struct sh_sir_self *self, int phase)
449 {
450 u16 uart5 = 0;
451 u16 uart0 = 0;
452
453 switch (phase) {
454 case TX_PHASE:
455 uart5 = TBEIM;
456 uart0 = TBEC | TIE;
457 break;
458 case TX_COMP_PHASE:
459 uart5 = TSBEIM;
460 uart0 = TIE;
461 break;
462 case RX_PHASE:
463 uart5 = RX_MASK;
464 uart0 = RIE;
465 break;
466 default:
467 break;
468 }
469
470 sh_sir_write(self, IRIF_UART5, uart5);
471 sh_sir_write(self, IRIF_UART0, uart0);
472 }
473
sh_sir_is_which_phase(struct sh_sir_self * self)474 static int sh_sir_is_which_phase(struct sh_sir_self *self)
475 {
476 u16 val = sh_sir_read(self, IRIF_UART5);
477
478 if (val & TBEIM)
479 return TX_PHASE;
480
481 if (val & TSBEIM)
482 return TX_COMP_PHASE;
483
484 if (val & RX_MASK)
485 return RX_PHASE;
486
487 return NONE_PHASE;
488 }
489
sh_sir_tx(struct sh_sir_self * self,int phase)490 static void sh_sir_tx(struct sh_sir_self *self, int phase)
491 {
492 switch (phase) {
493 case TX_PHASE:
494 if (0 >= self->tx_buff.len) {
495 sh_sir_set_phase(self, TX_COMP_PHASE);
496 } else {
497 sh_sir_write(self, IRIF_UART3, self->tx_buff.data[0]);
498 self->tx_buff.len--;
499 self->tx_buff.data++;
500 }
501 break;
502 case TX_COMP_PHASE:
503 sh_sir_set_phase(self, RX_PHASE);
504 netif_wake_queue(self->ndev);
505 break;
506 default:
507 dev_err(&self->ndev->dev, "should not happen\n");
508 break;
509 }
510 }
511
sh_sir_read_data(struct sh_sir_self * self)512 static int sh_sir_read_data(struct sh_sir_self *self)
513 {
514 u16 val;
515 int timeout = 1024;
516
517 while (timeout--) {
518 val = sh_sir_read(self, IRIF_UART1);
519
520 /* data get */
521 if (val & RBF) {
522 if (val & (URSME | UROVE | URFRE | URPRE))
523 break;
524
525 return (int)sh_sir_read(self, IRIF_UART4);
526 }
527
528 udelay(1);
529 }
530
531 dev_err(&self->ndev->dev, "UART1 %04x : STATUS %04x\n",
532 val, sh_sir_read(self, IRIF_UART_STS2));
533
534 /* read data register for clear error */
535 sh_sir_read(self, IRIF_UART4);
536
537 return -1;
538 }
539
sh_sir_rx(struct sh_sir_self * self)540 static void sh_sir_rx(struct sh_sir_self *self)
541 {
542 int timeout = 1024;
543 int data;
544
545 while (timeout--) {
546 data = sh_sir_read_data(self);
547 if (data < 0)
548 break;
549
550 async_unwrap_char(self->ndev, &self->ndev->stats,
551 &self->rx_buff, (u8)data);
552 self->ndev->last_rx = jiffies;
553
554 if (EOFD & sh_sir_read(self, IRIF_SIR_FRM))
555 continue;
556
557 break;
558 }
559 }
560
sh_sir_irq(int irq,void * dev_id)561 static irqreturn_t sh_sir_irq(int irq, void *dev_id)
562 {
563 struct sh_sir_self *self = dev_id;
564 struct device *dev = &self->ndev->dev;
565 int phase = sh_sir_is_which_phase(self);
566
567 switch (phase) {
568 case TX_COMP_PHASE:
569 case TX_PHASE:
570 sh_sir_tx(self, phase);
571 break;
572 case RX_PHASE:
573 if (sh_sir_read(self, IRIF_SIR3))
574 dev_err(dev, "rcv pulse width error occurred\n");
575
576 sh_sir_rx(self);
577 sh_sir_clear_all_err(self);
578 break;
579 default:
580 dev_err(dev, "unknown interrupt\n");
581 }
582
583 return IRQ_HANDLED;
584 }
585
586 /************************************************************************
587
588
589 net_device_ops function
590
591
592 ************************************************************************/
sh_sir_hard_xmit(struct sk_buff * skb,struct net_device * ndev)593 static int sh_sir_hard_xmit(struct sk_buff *skb, struct net_device *ndev)
594 {
595 struct sh_sir_self *self = netdev_priv(ndev);
596 int speed = irda_get_next_speed(skb);
597
598 if ((0 < speed) &&
599 (9600 != speed)) {
600 dev_err(&ndev->dev, "support 9600 only (%d)\n", speed);
601 return -EIO;
602 }
603
604 netif_stop_queue(ndev);
605
606 self->tx_buff.data = self->tx_buff.head;
607 self->tx_buff.len = 0;
608 if (skb->len)
609 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
610 self->tx_buff.truesize);
611
612 sh_sir_set_phase(self, TX_PHASE);
613 dev_kfree_skb(skb);
614
615 return 0;
616 }
617
sh_sir_ioctl(struct net_device * ndev,struct ifreq * ifreq,int cmd)618 static int sh_sir_ioctl(struct net_device *ndev, struct ifreq *ifreq, int cmd)
619 {
620 /*
621 * FIXME
622 *
623 * This function is needed for irda framework.
624 * But nothing to do now
625 */
626 return 0;
627 }
628
sh_sir_stats(struct net_device * ndev)629 static struct net_device_stats *sh_sir_stats(struct net_device *ndev)
630 {
631 struct sh_sir_self *self = netdev_priv(ndev);
632
633 return &self->ndev->stats;
634 }
635
sh_sir_open(struct net_device * ndev)636 static int sh_sir_open(struct net_device *ndev)
637 {
638 struct sh_sir_self *self = netdev_priv(ndev);
639 int err;
640
641 clk_enable(self->clk);
642 err = sh_sir_crc_init(self);
643 if (err)
644 goto open_err;
645
646 sh_sir_set_baudrate(self, 9600);
647
648 self->irlap = irlap_open(ndev, &self->qos, DRIVER_NAME);
649 if (!self->irlap) {
650 err = -ENODEV;
651 goto open_err;
652 }
653
654 /*
655 * Now enable the interrupt then start the queue
656 */
657 sh_sir_update_bits(self, IRIF_SIR_FRM, FRP, FRP);
658 sh_sir_read(self, IRIF_UART1); /* flag clear */
659 sh_sir_read(self, IRIF_UART4); /* flag clear */
660 sh_sir_set_phase(self, RX_PHASE);
661
662 netif_start_queue(ndev);
663
664 dev_info(&self->ndev->dev, "opened\n");
665
666 return 0;
667
668 open_err:
669 clk_disable(self->clk);
670
671 return err;
672 }
673
sh_sir_stop(struct net_device * ndev)674 static int sh_sir_stop(struct net_device *ndev)
675 {
676 struct sh_sir_self *self = netdev_priv(ndev);
677
678 /* Stop IrLAP */
679 if (self->irlap) {
680 irlap_close(self->irlap);
681 self->irlap = NULL;
682 }
683
684 netif_stop_queue(ndev);
685
686 dev_info(&ndev->dev, "stoped\n");
687
688 return 0;
689 }
690
691 static const struct net_device_ops sh_sir_ndo = {
692 .ndo_open = sh_sir_open,
693 .ndo_stop = sh_sir_stop,
694 .ndo_start_xmit = sh_sir_hard_xmit,
695 .ndo_do_ioctl = sh_sir_ioctl,
696 .ndo_get_stats = sh_sir_stats,
697 };
698
699 /************************************************************************
700
701
702 platform_driver function
703
704
705 ************************************************************************/
sh_sir_probe(struct platform_device * pdev)706 static int __devinit sh_sir_probe(struct platform_device *pdev)
707 {
708 struct net_device *ndev;
709 struct sh_sir_self *self;
710 struct resource *res;
711 char clk_name[8];
712 int irq;
713 int err = -ENOMEM;
714
715 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
716 irq = platform_get_irq(pdev, 0);
717 if (!res || irq < 0) {
718 dev_err(&pdev->dev, "Not enough platform resources.\n");
719 goto exit;
720 }
721
722 ndev = alloc_irdadev(sizeof(*self));
723 if (!ndev)
724 goto exit;
725
726 self = netdev_priv(ndev);
727 self->membase = ioremap_nocache(res->start, resource_size(res));
728 if (!self->membase) {
729 err = -ENXIO;
730 dev_err(&pdev->dev, "Unable to ioremap.\n");
731 goto err_mem_1;
732 }
733
734 err = sh_sir_init_iobuf(self, IRDA_SKB_MAX_MTU, IRDA_SIR_MAX_FRAME);
735 if (err)
736 goto err_mem_2;
737
738 snprintf(clk_name, sizeof(clk_name), "irda%d", pdev->id);
739 self->clk = clk_get(&pdev->dev, clk_name);
740 if (IS_ERR(self->clk)) {
741 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
742 goto err_mem_3;
743 }
744
745 irda_init_max_qos_capabilies(&self->qos);
746
747 ndev->netdev_ops = &sh_sir_ndo;
748 ndev->irq = irq;
749
750 self->ndev = ndev;
751 self->qos.baud_rate.bits &= IR_9600; /* FIXME */
752 self->qos.min_turn_time.bits = 1; /* 10 ms or more */
753
754 irda_qos_bits_to_value(&self->qos);
755
756 err = register_netdev(ndev);
757 if (err)
758 goto err_mem_4;
759
760 platform_set_drvdata(pdev, ndev);
761
762 if (request_irq(irq, sh_sir_irq, IRQF_DISABLED, "sh_sir", self)) {
763 dev_warn(&pdev->dev, "Unable to attach sh_sir interrupt\n");
764 goto err_mem_4;
765 }
766
767 dev_info(&pdev->dev, "SuperH IrDA probed\n");
768
769 goto exit;
770
771 err_mem_4:
772 clk_put(self->clk);
773 err_mem_3:
774 sh_sir_remove_iobuf(self);
775 err_mem_2:
776 iounmap(self->membase);
777 err_mem_1:
778 free_netdev(ndev);
779 exit:
780 return err;
781 }
782
sh_sir_remove(struct platform_device * pdev)783 static int __devexit sh_sir_remove(struct platform_device *pdev)
784 {
785 struct net_device *ndev = platform_get_drvdata(pdev);
786 struct sh_sir_self *self = netdev_priv(ndev);
787
788 if (!self)
789 return 0;
790
791 unregister_netdev(ndev);
792 clk_put(self->clk);
793 sh_sir_remove_iobuf(self);
794 iounmap(self->membase);
795 free_netdev(ndev);
796 platform_set_drvdata(pdev, NULL);
797
798 return 0;
799 }
800
801 static struct platform_driver sh_sir_driver = {
802 .probe = sh_sir_probe,
803 .remove = __devexit_p(sh_sir_remove),
804 .driver = {
805 .name = DRIVER_NAME,
806 },
807 };
808
sh_sir_init(void)809 static int __init sh_sir_init(void)
810 {
811 return platform_driver_register(&sh_sir_driver);
812 }
813
sh_sir_exit(void)814 static void __exit sh_sir_exit(void)
815 {
816 platform_driver_unregister(&sh_sir_driver);
817 }
818
819 module_init(sh_sir_init);
820 module_exit(sh_sir_exit);
821
822 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
823 MODULE_DESCRIPTION("SuperH IrDA driver");
824 MODULE_LICENSE("GPL");
825