1 /*
2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __CHELSIO_COMMON_H
33 #define __CHELSIO_COMMON_H
34
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/ctype.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/netdevice.h>
41 #include <linux/ethtool.h>
42 #include <linux/mdio.h>
43 #include "version.h"
44
45 #define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__)
46 #define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__)
47 #define CH_ALERT(adap, fmt, ...) \
48 dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__)
49
50 /*
51 * More powerful macro that selectively prints messages based on msg_enable.
52 * For info and debugging messages.
53 */
54 #define CH_MSG(adapter, level, category, fmt, ...) do { \
55 if ((adapter)->msg_enable & NETIF_MSG_##category) \
56 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
57 ## __VA_ARGS__); \
58 } while (0)
59
60 #ifdef DEBUG
61 # define CH_DBG(adapter, category, fmt, ...) \
62 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
63 #else
64 # define CH_DBG(adapter, category, fmt, ...)
65 #endif
66
67 /* Additional NETIF_MSG_* categories */
68 #define NETIF_MSG_MMIO 0x8000000
69
70 enum {
71 MAX_NPORTS = 2, /* max # of ports */
72 MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
73 EEPROMSIZE = 8192, /* Serial EEPROM size */
74 SERNUM_LEN = 16, /* Serial # length */
75 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
76 TCB_SIZE = 128, /* TCB size */
77 NMTUS = 16, /* size of MTU table */
78 NCCTRL_WIN = 32, /* # of congestion control windows */
79 PROTO_SRAM_LINES = 128, /* size of TP sram */
80 };
81
82 #define MAX_RX_COALESCING_LEN 12288U
83
84 enum {
85 PAUSE_RX = 1 << 0,
86 PAUSE_TX = 1 << 1,
87 PAUSE_AUTONEG = 1 << 2
88 };
89
90 enum {
91 SUPPORTED_IRQ = 1 << 24
92 };
93
94 enum { /* adapter interrupt-maintained statistics */
95 STAT_ULP_CH0_PBL_OOB,
96 STAT_ULP_CH1_PBL_OOB,
97 STAT_PCI_CORR_ECC,
98
99 IRQ_NUM_STATS /* keep last */
100 };
101
102 #define TP_VERSION_MAJOR 1
103 #define TP_VERSION_MINOR 1
104 #define TP_VERSION_MICRO 0
105
106 #define S_TP_VERSION_MAJOR 16
107 #define M_TP_VERSION_MAJOR 0xFF
108 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
109 #define G_TP_VERSION_MAJOR(x) \
110 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
111
112 #define S_TP_VERSION_MINOR 8
113 #define M_TP_VERSION_MINOR 0xFF
114 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR)
115 #define G_TP_VERSION_MINOR(x) \
116 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
117
118 #define S_TP_VERSION_MICRO 0
119 #define M_TP_VERSION_MICRO 0xFF
120 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
121 #define G_TP_VERSION_MICRO(x) \
122 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
123
124 enum {
125 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
126 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
127 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
128 };
129
130 enum sge_context_type { /* SGE egress context types */
131 SGE_CNTXT_RDMA = 0,
132 SGE_CNTXT_ETH = 2,
133 SGE_CNTXT_OFLD = 4,
134 SGE_CNTXT_CTRL = 5
135 };
136
137 enum {
138 AN_PKT_SIZE = 32, /* async notification packet size */
139 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
140 };
141
142 struct sg_ent { /* SGE scatter/gather entry */
143 __be32 len[2];
144 __be64 addr[2];
145 };
146
147 #ifndef SGE_NUM_GENBITS
148 /* Must be 1 or 2 */
149 # define SGE_NUM_GENBITS 2
150 #endif
151
152 #define TX_DESC_FLITS 16U
153 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
154
155 struct cphy;
156 struct adapter;
157
158 struct mdio_ops {
159 int (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
160 u16 reg_addr);
161 int (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
162 u16 reg_addr, u16 val);
163 unsigned mode_support;
164 };
165
166 struct adapter_info {
167 unsigned char nports0; /* # of ports on channel 0 */
168 unsigned char nports1; /* # of ports on channel 1 */
169 unsigned char phy_base_addr; /* MDIO PHY base address */
170 unsigned int gpio_out; /* GPIO output settings */
171 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */
172 unsigned long caps; /* adapter capabilities */
173 const struct mdio_ops *mdio_ops; /* MDIO operations */
174 const char *desc; /* product description */
175 };
176
177 struct mc5_stats {
178 unsigned long parity_err;
179 unsigned long active_rgn_full;
180 unsigned long nfa_srch_err;
181 unsigned long unknown_cmd;
182 unsigned long reqq_parity_err;
183 unsigned long dispq_parity_err;
184 unsigned long del_act_empty;
185 };
186
187 struct mc7_stats {
188 unsigned long corr_err;
189 unsigned long uncorr_err;
190 unsigned long parity_err;
191 unsigned long addr_err;
192 };
193
194 struct mac_stats {
195 u64 tx_octets; /* total # of octets in good frames */
196 u64 tx_octets_bad; /* total # of octets in error frames */
197 u64 tx_frames; /* all good frames */
198 u64 tx_mcast_frames; /* good multicast frames */
199 u64 tx_bcast_frames; /* good broadcast frames */
200 u64 tx_pause; /* # of transmitted pause frames */
201 u64 tx_deferred; /* frames with deferred transmissions */
202 u64 tx_late_collisions; /* # of late collisions */
203 u64 tx_total_collisions; /* # of total collisions */
204 u64 tx_excess_collisions; /* frame errors from excessive collissions */
205 u64 tx_underrun; /* # of Tx FIFO underruns */
206 u64 tx_len_errs; /* # of Tx length errors */
207 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
208 u64 tx_excess_deferral; /* # of frames with excessive deferral */
209 u64 tx_fcs_errs; /* # of frames with bad FCS */
210
211 u64 tx_frames_64; /* # of Tx frames in a particular range */
212 u64 tx_frames_65_127;
213 u64 tx_frames_128_255;
214 u64 tx_frames_256_511;
215 u64 tx_frames_512_1023;
216 u64 tx_frames_1024_1518;
217 u64 tx_frames_1519_max;
218
219 u64 rx_octets; /* total # of octets in good frames */
220 u64 rx_octets_bad; /* total # of octets in error frames */
221 u64 rx_frames; /* all good frames */
222 u64 rx_mcast_frames; /* good multicast frames */
223 u64 rx_bcast_frames; /* good broadcast frames */
224 u64 rx_pause; /* # of received pause frames */
225 u64 rx_fcs_errs; /* # of received frames with bad FCS */
226 u64 rx_align_errs; /* alignment errors */
227 u64 rx_symbol_errs; /* symbol errors */
228 u64 rx_data_errs; /* data errors */
229 u64 rx_sequence_errs; /* sequence errors */
230 u64 rx_runt; /* # of runt frames */
231 u64 rx_jabber; /* # of jabber frames */
232 u64 rx_short; /* # of short frames */
233 u64 rx_too_long; /* # of oversized frames */
234 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
235
236 u64 rx_frames_64; /* # of Rx frames in a particular range */
237 u64 rx_frames_65_127;
238 u64 rx_frames_128_255;
239 u64 rx_frames_256_511;
240 u64 rx_frames_512_1023;
241 u64 rx_frames_1024_1518;
242 u64 rx_frames_1519_max;
243
244 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
245
246 unsigned long tx_fifo_parity_err;
247 unsigned long rx_fifo_parity_err;
248 unsigned long tx_fifo_urun;
249 unsigned long rx_fifo_ovfl;
250 unsigned long serdes_signal_loss;
251 unsigned long xaui_pcs_ctc_err;
252 unsigned long xaui_pcs_align_change;
253
254 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
255 unsigned long num_resets; /* # times reset due to stuck TX */
256
257 unsigned long link_faults; /* # detected link faults */
258 };
259
260 struct tp_mib_stats {
261 u32 ipInReceive_hi;
262 u32 ipInReceive_lo;
263 u32 ipInHdrErrors_hi;
264 u32 ipInHdrErrors_lo;
265 u32 ipInAddrErrors_hi;
266 u32 ipInAddrErrors_lo;
267 u32 ipInUnknownProtos_hi;
268 u32 ipInUnknownProtos_lo;
269 u32 ipInDiscards_hi;
270 u32 ipInDiscards_lo;
271 u32 ipInDelivers_hi;
272 u32 ipInDelivers_lo;
273 u32 ipOutRequests_hi;
274 u32 ipOutRequests_lo;
275 u32 ipOutDiscards_hi;
276 u32 ipOutDiscards_lo;
277 u32 ipOutNoRoutes_hi;
278 u32 ipOutNoRoutes_lo;
279 u32 ipReasmTimeout;
280 u32 ipReasmReqds;
281 u32 ipReasmOKs;
282 u32 ipReasmFails;
283
284 u32 reserved[8];
285
286 u32 tcpActiveOpens;
287 u32 tcpPassiveOpens;
288 u32 tcpAttemptFails;
289 u32 tcpEstabResets;
290 u32 tcpOutRsts;
291 u32 tcpCurrEstab;
292 u32 tcpInSegs_hi;
293 u32 tcpInSegs_lo;
294 u32 tcpOutSegs_hi;
295 u32 tcpOutSegs_lo;
296 u32 tcpRetransSeg_hi;
297 u32 tcpRetransSeg_lo;
298 u32 tcpInErrs_hi;
299 u32 tcpInErrs_lo;
300 u32 tcpRtoMin;
301 u32 tcpRtoMax;
302 };
303
304 struct tp_params {
305 unsigned int nchan; /* # of channels */
306 unsigned int pmrx_size; /* total PMRX capacity */
307 unsigned int pmtx_size; /* total PMTX capacity */
308 unsigned int cm_size; /* total CM capacity */
309 unsigned int chan_rx_size; /* per channel Rx size */
310 unsigned int chan_tx_size; /* per channel Tx size */
311 unsigned int rx_pg_size; /* Rx page size */
312 unsigned int tx_pg_size; /* Tx page size */
313 unsigned int rx_num_pgs; /* # of Rx pages */
314 unsigned int tx_num_pgs; /* # of Tx pages */
315 unsigned int ntimer_qs; /* # of timer queues */
316 };
317
318 struct qset_params { /* SGE queue set parameters */
319 unsigned int polling; /* polling/interrupt service for rspq */
320 unsigned int lro; /* large receive offload */
321 unsigned int coalesce_usecs; /* irq coalescing timer */
322 unsigned int rspq_size; /* # of entries in response queue */
323 unsigned int fl_size; /* # of entries in regular free list */
324 unsigned int jumbo_size; /* # of entries in jumbo free list */
325 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
326 unsigned int cong_thres; /* FL congestion threshold */
327 unsigned int vector; /* Interrupt (line or vector) number */
328 };
329
330 struct sge_params {
331 unsigned int max_pkt_size; /* max offload pkt size */
332 struct qset_params qset[SGE_QSETS];
333 };
334
335 struct mc5_params {
336 unsigned int mode; /* selects MC5 width */
337 unsigned int nservers; /* size of server region */
338 unsigned int nfilters; /* size of filter region */
339 unsigned int nroutes; /* size of routing region */
340 };
341
342 /* Default MC5 region sizes */
343 enum {
344 DEFAULT_NSERVERS = 512,
345 DEFAULT_NFILTERS = 128
346 };
347
348 /* MC5 modes, these must be non-0 */
349 enum {
350 MC5_MODE_144_BIT = 1,
351 MC5_MODE_72_BIT = 2
352 };
353
354 /* MC5 min active region size */
355 enum { MC5_MIN_TIDS = 16 };
356
357 struct vpd_params {
358 unsigned int cclk;
359 unsigned int mclk;
360 unsigned int uclk;
361 unsigned int mdc;
362 unsigned int mem_timing;
363 u8 sn[SERNUM_LEN + 1];
364 u8 eth_base[6];
365 u8 port_type[MAX_NPORTS];
366 unsigned short xauicfg[2];
367 };
368
369 struct pci_params {
370 unsigned int vpd_cap_addr;
371 unsigned int pcie_cap_addr;
372 unsigned short speed;
373 unsigned char width;
374 unsigned char variant;
375 };
376
377 enum {
378 PCI_VARIANT_PCI,
379 PCI_VARIANT_PCIX_MODE1_PARITY,
380 PCI_VARIANT_PCIX_MODE1_ECC,
381 PCI_VARIANT_PCIX_266_MODE2,
382 PCI_VARIANT_PCIE
383 };
384
385 struct adapter_params {
386 struct sge_params sge;
387 struct mc5_params mc5;
388 struct tp_params tp;
389 struct vpd_params vpd;
390 struct pci_params pci;
391
392 const struct adapter_info *info;
393
394 unsigned short mtus[NMTUS];
395 unsigned short a_wnd[NCCTRL_WIN];
396 unsigned short b_wnd[NCCTRL_WIN];
397
398 unsigned int nports; /* # of ethernet ports */
399 unsigned int chan_map; /* bitmap of in-use Tx channels */
400 unsigned int stats_update_period; /* MAC stats accumulation period */
401 unsigned int linkpoll_period; /* link poll period in 0.1s */
402 unsigned int rev; /* chip revision */
403 unsigned int offload;
404 };
405
406 enum { /* chip revisions */
407 T3_REV_A = 0,
408 T3_REV_B = 2,
409 T3_REV_B2 = 3,
410 T3_REV_C = 4,
411 };
412
413 struct trace_params {
414 u32 sip;
415 u32 sip_mask;
416 u32 dip;
417 u32 dip_mask;
418 u16 sport;
419 u16 sport_mask;
420 u16 dport;
421 u16 dport_mask;
422 u32 vlan:12;
423 u32 vlan_mask:12;
424 u32 intf:4;
425 u32 intf_mask:4;
426 u8 proto;
427 u8 proto_mask;
428 };
429
430 struct link_config {
431 unsigned int supported; /* link capabilities */
432 unsigned int advertising; /* advertised capabilities */
433 unsigned short requested_speed; /* speed user has requested */
434 unsigned short speed; /* actual link speed */
435 unsigned char requested_duplex; /* duplex user has requested */
436 unsigned char duplex; /* actual link duplex */
437 unsigned char requested_fc; /* flow control user has requested */
438 unsigned char fc; /* actual link flow control */
439 unsigned char autoneg; /* autonegotiating? */
440 unsigned int link_ok; /* link up? */
441 };
442
443 #define SPEED_INVALID 0xffff
444 #define DUPLEX_INVALID 0xff
445
446 struct mc5 {
447 struct adapter *adapter;
448 unsigned int tcam_size;
449 unsigned char part_type;
450 unsigned char parity_enabled;
451 unsigned char mode;
452 struct mc5_stats stats;
453 };
454
t3_mc5_size(const struct mc5 * p)455 static inline unsigned int t3_mc5_size(const struct mc5 *p)
456 {
457 return p->tcam_size;
458 }
459
460 struct mc7 {
461 struct adapter *adapter; /* backpointer to adapter */
462 unsigned int size; /* memory size in bytes */
463 unsigned int width; /* MC7 interface width */
464 unsigned int offset; /* register address offset for MC7 instance */
465 const char *name; /* name of MC7 instance */
466 struct mc7_stats stats; /* MC7 statistics */
467 };
468
t3_mc7_size(const struct mc7 * p)469 static inline unsigned int t3_mc7_size(const struct mc7 *p)
470 {
471 return p->size;
472 }
473
474 struct cmac {
475 struct adapter *adapter;
476 unsigned int offset;
477 unsigned int nucast; /* # of address filters for unicast MACs */
478 unsigned int tx_tcnt;
479 unsigned int tx_xcnt;
480 u64 tx_mcnt;
481 unsigned int rx_xcnt;
482 unsigned int rx_ocnt;
483 u64 rx_mcnt;
484 unsigned int toggle_cnt;
485 unsigned int txen;
486 u64 rx_pause;
487 struct mac_stats stats;
488 };
489
490 enum {
491 MAC_DIRECTION_RX = 1,
492 MAC_DIRECTION_TX = 2,
493 MAC_RXFIFO_SIZE = 32768
494 };
495
496 /* PHY loopback direction */
497 enum {
498 PHY_LOOPBACK_TX = 1,
499 PHY_LOOPBACK_RX = 2
500 };
501
502 /* PHY interrupt types */
503 enum {
504 cphy_cause_link_change = 1,
505 cphy_cause_fifo_error = 2,
506 cphy_cause_module_change = 4,
507 };
508
509 /* PHY module types */
510 enum {
511 phy_modtype_none,
512 phy_modtype_sr,
513 phy_modtype_lr,
514 phy_modtype_lrm,
515 phy_modtype_twinax,
516 phy_modtype_twinax_long,
517 phy_modtype_unknown
518 };
519
520 /* PHY operations */
521 struct cphy_ops {
522 int (*reset)(struct cphy *phy, int wait);
523
524 int (*intr_enable)(struct cphy *phy);
525 int (*intr_disable)(struct cphy *phy);
526 int (*intr_clear)(struct cphy *phy);
527 int (*intr_handler)(struct cphy *phy);
528
529 int (*autoneg_enable)(struct cphy *phy);
530 int (*autoneg_restart)(struct cphy *phy);
531
532 int (*advertise)(struct cphy *phy, unsigned int advertise_map);
533 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
534 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
535 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
536 int *duplex, int *fc);
537 int (*power_down)(struct cphy *phy, int enable);
538
539 u32 mmds;
540 };
541 enum {
542 EDC_OPT_AEL2005 = 0,
543 EDC_OPT_AEL2005_SIZE = 1084,
544 EDC_TWX_AEL2005 = 1,
545 EDC_TWX_AEL2005_SIZE = 1464,
546 EDC_TWX_AEL2020 = 2,
547 EDC_TWX_AEL2020_SIZE = 1628,
548 EDC_MAX_SIZE = EDC_TWX_AEL2020_SIZE, /* Max cache size */
549 };
550
551 /* A PHY instance */
552 struct cphy {
553 u8 modtype; /* PHY module type */
554 short priv; /* scratch pad */
555 unsigned int caps; /* PHY capabilities */
556 struct adapter *adapter; /* associated adapter */
557 const char *desc; /* PHY description */
558 unsigned long fifo_errors; /* FIFO over/under-flows */
559 const struct cphy_ops *ops; /* PHY operations */
560 struct mdio_if_info mdio;
561 u16 phy_cache[EDC_MAX_SIZE]; /* EDC cache */
562 };
563
564 /* Convenience MDIO read/write wrappers */
t3_mdio_read(struct cphy * phy,int mmd,int reg,unsigned int * valp)565 static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg,
566 unsigned int *valp)
567 {
568 int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg);
569 *valp = (rc >= 0) ? rc : -1;
570 return (rc >= 0) ? 0 : rc;
571 }
572
t3_mdio_write(struct cphy * phy,int mmd,int reg,unsigned int val)573 static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg,
574 unsigned int val)
575 {
576 return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd,
577 reg, val);
578 }
579
580 /* Convenience initializer */
cphy_init(struct cphy * phy,struct adapter * adapter,int phy_addr,struct cphy_ops * phy_ops,const struct mdio_ops * mdio_ops,unsigned int caps,const char * desc)581 static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
582 int phy_addr, struct cphy_ops *phy_ops,
583 const struct mdio_ops *mdio_ops,
584 unsigned int caps, const char *desc)
585 {
586 phy->caps = caps;
587 phy->adapter = adapter;
588 phy->desc = desc;
589 phy->ops = phy_ops;
590 if (mdio_ops) {
591 phy->mdio.prtad = phy_addr;
592 phy->mdio.mmds = phy_ops->mmds;
593 phy->mdio.mode_support = mdio_ops->mode_support;
594 phy->mdio.mdio_read = mdio_ops->read;
595 phy->mdio.mdio_write = mdio_ops->write;
596 }
597 }
598
599 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
600 #define MAC_STATS_ACCUM_SECS 180
601
602 #define XGM_REG(reg_addr, idx) \
603 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
604
605 struct addr_val_pair {
606 unsigned int reg_addr;
607 unsigned int val;
608 };
609
610 #include "adapter.h"
611
612 #ifndef PCI_VENDOR_ID_CHELSIO
613 # define PCI_VENDOR_ID_CHELSIO 0x1425
614 #endif
615
616 #define for_each_port(adapter, iter) \
617 for (iter = 0; iter < (adapter)->params.nports; ++iter)
618
619 #define adapter_info(adap) ((adap)->params.info)
620
uses_xaui(const struct adapter * adap)621 static inline int uses_xaui(const struct adapter *adap)
622 {
623 return adapter_info(adap)->caps & SUPPORTED_AUI;
624 }
625
is_10G(const struct adapter * adap)626 static inline int is_10G(const struct adapter *adap)
627 {
628 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
629 }
630
is_offload(const struct adapter * adap)631 static inline int is_offload(const struct adapter *adap)
632 {
633 return adap->params.offload;
634 }
635
core_ticks_per_usec(const struct adapter * adap)636 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
637 {
638 return adap->params.vpd.cclk / 1000;
639 }
640
is_pcie(const struct adapter * adap)641 static inline unsigned int is_pcie(const struct adapter *adap)
642 {
643 return adap->params.pci.variant == PCI_VARIANT_PCIE;
644 }
645
646 void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
647 u32 val);
648 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
649 int n, unsigned int offset);
650 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
651 int polarity, int attempts, int delay, u32 *valp);
t3_wait_op_done(struct adapter * adapter,int reg,u32 mask,int polarity,int attempts,int delay)652 static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask,
653 int polarity, int attempts, int delay)
654 {
655 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
656 delay, NULL);
657 }
658 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
659 unsigned int set);
660 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
661 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
662 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
663 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
664 int t3_phy_lasi_intr_enable(struct cphy *phy);
665 int t3_phy_lasi_intr_disable(struct cphy *phy);
666 int t3_phy_lasi_intr_clear(struct cphy *phy);
667 int t3_phy_lasi_intr_handler(struct cphy *phy);
668
669 void t3_intr_enable(struct adapter *adapter);
670 void t3_intr_disable(struct adapter *adapter);
671 void t3_intr_clear(struct adapter *adapter);
672 void t3_xgm_intr_enable(struct adapter *adapter, int idx);
673 void t3_xgm_intr_disable(struct adapter *adapter, int idx);
674 void t3_port_intr_enable(struct adapter *adapter, int idx);
675 void t3_port_intr_disable(struct adapter *adapter, int idx);
676 int t3_slow_intr_handler(struct adapter *adapter);
677 int t3_phy_intr_handler(struct adapter *adapter);
678
679 void t3_link_changed(struct adapter *adapter, int port_id);
680 void t3_link_fault(struct adapter *adapter, int port_id);
681 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
682 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
683 int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data);
684 int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data);
685 int t3_seeprom_wp(struct adapter *adapter, int enable);
686 int t3_get_tp_version(struct adapter *adapter, u32 *vers);
687 int t3_check_tpsram_version(struct adapter *adapter);
688 int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram,
689 unsigned int size);
690 int t3_set_proto_sram(struct adapter *adap, const u8 *data);
691 int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);
692 int t3_get_fw_version(struct adapter *adapter, u32 *vers);
693 int t3_check_fw_version(struct adapter *adapter);
694 int t3_init_hw(struct adapter *adapter, u32 fw_params);
695 int t3_reset_adapter(struct adapter *adapter);
696 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
697 int reset);
698 int t3_replay_prep_adapter(struct adapter *adapter);
699 void t3_led_ready(struct adapter *adapter);
700 void t3_fatal_err(struct adapter *adapter);
701 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
702 void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
703 const u8 * cpus, const u16 *rspq);
704 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
705 unsigned int n, unsigned int *valp);
706 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
707 u64 *buf);
708
709 int t3_mac_reset(struct cmac *mac);
710 void t3b_pcs_reset(struct cmac *mac);
711 void t3_mac_disable_exact_filters(struct cmac *mac);
712 void t3_mac_enable_exact_filters(struct cmac *mac);
713 int t3_mac_enable(struct cmac *mac, int which);
714 int t3_mac_disable(struct cmac *mac, int which);
715 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
716 int t3_mac_set_rx_mode(struct cmac *mac, struct net_device *dev);
717 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
718 int t3_mac_set_num_ucast(struct cmac *mac, int n);
719 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
720 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
721 int t3b2_mac_watchdog_task(struct cmac *mac);
722
723 void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
724 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
725 unsigned int nroutes);
726 void t3_mc5_intr_handler(struct mc5 *mc5);
727
728 void t3_tp_set_offload_mode(struct adapter *adap, int enable);
729 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps);
730 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
731 unsigned short alpha[NCCTRL_WIN],
732 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
733 void t3_config_trace_filter(struct adapter *adapter,
734 const struct trace_params *tp, int filter_index,
735 int invert, int enable);
736 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched);
737
738 void t3_sge_prep(struct adapter *adap, struct sge_params *p);
739 void t3_sge_init(struct adapter *adap, struct sge_params *p);
740 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
741 enum sge_context_type type, int respq, u64 base_addr,
742 unsigned int size, unsigned int token, int gen,
743 unsigned int cidx);
744 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
745 int gts_enable, u64 base_addr, unsigned int size,
746 unsigned int esize, unsigned int cong_thres, int gen,
747 unsigned int cidx);
748 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
749 int irq_vec_idx, u64 base_addr, unsigned int size,
750 unsigned int fl_thres, int gen, unsigned int cidx);
751 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
752 unsigned int size, int rspq, int ovfl_mode,
753 unsigned int credits, unsigned int credit_thres);
754 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable);
755 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id);
756 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id);
757 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id);
758 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
759 unsigned int credits);
760
761 int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
762 int phy_addr, const struct mdio_ops *mdio_ops);
763 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
764 int phy_addr, const struct mdio_ops *mdio_ops);
765 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
766 int phy_addr, const struct mdio_ops *mdio_ops);
767 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
768 int phy_addr, const struct mdio_ops *mdio_ops);
769 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter,
770 int phy_addr, const struct mdio_ops *mdio_ops);
771 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
772 const struct mdio_ops *mdio_ops);
773 int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
774 int phy_addr, const struct mdio_ops *mdio_ops);
775 int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter,
776 int phy_addr, const struct mdio_ops *mdio_ops);
777 #endif /* __CHELSIO_COMMON_H */
778