1 /*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include "drmP.h"
26 #include "nouveau_drv.h"
27 #include "nouveau_bios.h"
28 #include "nouveau_pm.h"
29
30 /*XXX: boards using limits 0x40 need fixing, the register layout
31 * is correct here, but, there's some other funny magic
32 * that modifies things, so it's not likely we'll set/read
33 * the correct timings yet.. working on it...
34 */
35
36 struct nva3_pm_state {
37 struct pll_lims pll;
38 int N, M, P;
39 };
40
41 int
nva3_pm_clock_get(struct drm_device * dev,u32 id)42 nva3_pm_clock_get(struct drm_device *dev, u32 id)
43 {
44 struct pll_lims pll;
45 int P, N, M, ret;
46 u32 reg;
47
48 ret = get_pll_limits(dev, id, &pll);
49 if (ret)
50 return ret;
51
52 reg = nv_rd32(dev, pll.reg + 4);
53 P = (reg & 0x003f0000) >> 16;
54 N = (reg & 0x0000ff00) >> 8;
55 M = (reg & 0x000000ff);
56 return pll.refclk * N / M / P;
57 }
58
59 void *
nva3_pm_clock_pre(struct drm_device * dev,struct nouveau_pm_level * perflvl,u32 id,int khz)60 nva3_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
61 u32 id, int khz)
62 {
63 struct nva3_pm_state *state;
64 int dummy, ret;
65
66 state = kzalloc(sizeof(*state), GFP_KERNEL);
67 if (!state)
68 return ERR_PTR(-ENOMEM);
69
70 ret = get_pll_limits(dev, id, &state->pll);
71 if (ret < 0) {
72 kfree(state);
73 return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
74 }
75
76 ret = nv50_calc_pll2(dev, &state->pll, khz, &state->N, &dummy,
77 &state->M, &state->P);
78 if (ret < 0) {
79 kfree(state);
80 return ERR_PTR(ret);
81 }
82
83 return state;
84 }
85
86 void
nva3_pm_clock_set(struct drm_device * dev,void * pre_state)87 nva3_pm_clock_set(struct drm_device *dev, void *pre_state)
88 {
89 struct nva3_pm_state *state = pre_state;
90 u32 reg = state->pll.reg;
91
92 nv_wr32(dev, reg + 4, (state->P << 16) | (state->N << 8) | state->M);
93 kfree(state);
94 }
95
96