1 /*
2 * pata_hpt3x3 - HPT3x3 driver
3 * (c) Copyright 2005-2006 Red Hat
4 *
5 * Was pata_hpt34x but the naming was confusing as it supported the
6 * 343 and 363 so it has been renamed.
7 *
8 * Based on:
9 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 *
12 * May be copied or modified under the terms of the GNU General Public
13 * License
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/blkdev.h>
21 #include <linux/delay.h>
22 #include <scsi/scsi_host.h>
23 #include <linux/libata.h>
24
25 #define DRV_NAME "pata_hpt3x3"
26 #define DRV_VERSION "0.6.1"
27
28 /**
29 * hpt3x3_set_piomode - PIO setup
30 * @ap: ATA interface
31 * @adev: device on the interface
32 *
33 * Set our PIO requirements. This is fairly simple on the HPT3x3 as
34 * all we have to do is clear the MWDMA and UDMA bits then load the
35 * mode number.
36 */
37
hpt3x3_set_piomode(struct ata_port * ap,struct ata_device * adev)38 static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
39 {
40 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
41 u32 r1, r2;
42 int dn = 2 * ap->port_no + adev->devno;
43
44 pci_read_config_dword(pdev, 0x44, &r1);
45 pci_read_config_dword(pdev, 0x48, &r2);
46 /* Load the PIO timing number */
47 r1 &= ~(7 << (3 * dn));
48 r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
49 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
50
51 pci_write_config_dword(pdev, 0x44, r1);
52 pci_write_config_dword(pdev, 0x48, r2);
53 }
54
55 #if defined(CONFIG_PATA_HPT3X3_DMA)
56 /**
57 * hpt3x3_set_dmamode - DMA timing setup
58 * @ap: ATA interface
59 * @adev: Device being configured
60 *
61 * Set up the channel for MWDMA or UDMA modes. Much the same as with
62 * PIO, load the mode number and then set MWDMA or UDMA flag.
63 *
64 * 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
65 * 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
66 */
67
hpt3x3_set_dmamode(struct ata_port * ap,struct ata_device * adev)68 static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
69 {
70 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
71 u32 r1, r2;
72 int dn = 2 * ap->port_no + adev->devno;
73 int mode_num = adev->dma_mode & 0x0F;
74
75 pci_read_config_dword(pdev, 0x44, &r1);
76 pci_read_config_dword(pdev, 0x48, &r2);
77 /* Load the timing number */
78 r1 &= ~(7 << (3 * dn));
79 r1 |= (mode_num << (3 * dn));
80 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
81
82 if (adev->dma_mode >= XFER_UDMA_0)
83 r2 |= (0x01 << dn); /* Ultra mode */
84 else
85 r2 |= (0x10 << dn); /* MWDMA */
86
87 pci_write_config_dword(pdev, 0x44, r1);
88 pci_write_config_dword(pdev, 0x48, r2);
89 }
90
91 /**
92 * hpt3x3_freeze - DMA workaround
93 * @ap: port to freeze
94 *
95 * When freezing an HPT3x3 we must stop any pending DMA before
96 * writing to the control register or the chip will hang
97 */
98
hpt3x3_freeze(struct ata_port * ap)99 static void hpt3x3_freeze(struct ata_port *ap)
100 {
101 void __iomem *mmio = ap->ioaddr.bmdma_addr;
102
103 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ ATA_DMA_START,
104 mmio + ATA_DMA_CMD);
105 ata_sff_dma_pause(ap);
106 ata_sff_freeze(ap);
107 }
108
109 /**
110 * hpt3x3_bmdma_setup - DMA workaround
111 * @qc: Queued command
112 *
113 * When issuing BMDMA we must clean up the error/active bits in
114 * software on this device
115 */
116
hpt3x3_bmdma_setup(struct ata_queued_cmd * qc)117 static void hpt3x3_bmdma_setup(struct ata_queued_cmd *qc)
118 {
119 struct ata_port *ap = qc->ap;
120 u8 r = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
121 r |= ATA_DMA_INTR | ATA_DMA_ERR;
122 iowrite8(r, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
123 return ata_bmdma_setup(qc);
124 }
125
126 /**
127 * hpt3x3_atapi_dma - ATAPI DMA check
128 * @qc: Queued command
129 *
130 * Just say no - we don't do ATAPI DMA
131 */
132
hpt3x3_atapi_dma(struct ata_queued_cmd * qc)133 static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
134 {
135 return 1;
136 }
137
138 #endif /* CONFIG_PATA_HPT3X3_DMA */
139
140 static struct scsi_host_template hpt3x3_sht = {
141 ATA_BMDMA_SHT(DRV_NAME),
142 };
143
144 static struct ata_port_operations hpt3x3_port_ops = {
145 .inherits = &ata_bmdma_port_ops,
146 .cable_detect = ata_cable_40wire,
147 .set_piomode = hpt3x3_set_piomode,
148 #if defined(CONFIG_PATA_HPT3X3_DMA)
149 .set_dmamode = hpt3x3_set_dmamode,
150 .bmdma_setup = hpt3x3_bmdma_setup,
151 .check_atapi_dma= hpt3x3_atapi_dma,
152 .freeze = hpt3x3_freeze,
153 #endif
154
155 };
156
157 /**
158 * hpt3x3_init_chipset - chip setup
159 * @dev: PCI device
160 *
161 * Perform the setup required at boot and on resume.
162 */
163
hpt3x3_init_chipset(struct pci_dev * dev)164 static void hpt3x3_init_chipset(struct pci_dev *dev)
165 {
166 u16 cmd;
167 /* Initialize the board */
168 pci_write_config_word(dev, 0x80, 0x00);
169 /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
170 pci_read_config_word(dev, PCI_COMMAND, &cmd);
171 if (cmd & PCI_COMMAND_MEMORY)
172 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
173 else
174 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
175 }
176
177 /**
178 * hpt3x3_init_one - Initialise an HPT343/363
179 * @pdev: PCI device
180 * @id: Entry in match table
181 *
182 * Perform basic initialisation. We set the device up so we access all
183 * ports via BAR4. This is necessary to work around errata.
184 */
185
hpt3x3_init_one(struct pci_dev * pdev,const struct pci_device_id * id)186 static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
187 {
188 static int printed_version;
189 static const struct ata_port_info info = {
190 .flags = ATA_FLAG_SLAVE_POSS,
191 .pio_mask = ATA_PIO4,
192 #if defined(CONFIG_PATA_HPT3X3_DMA)
193 /* Further debug needed */
194 .mwdma_mask = ATA_MWDMA2,
195 .udma_mask = ATA_UDMA2,
196 #endif
197 .port_ops = &hpt3x3_port_ops
198 };
199 /* Register offsets of taskfiles in BAR4 area */
200 static const u8 offset_cmd[2] = { 0x20, 0x28 };
201 static const u8 offset_ctl[2] = { 0x36, 0x3E };
202 const struct ata_port_info *ppi[] = { &info, NULL };
203 struct ata_host *host;
204 int i, rc;
205 void __iomem *base;
206
207 hpt3x3_init_chipset(pdev);
208
209 if (!printed_version++)
210 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
211
212 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
213 if (!host)
214 return -ENOMEM;
215 /* acquire resources and fill host */
216 rc = pcim_enable_device(pdev);
217 if (rc)
218 return rc;
219
220 /* Everything is relative to BAR4 if we set up this way */
221 rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
222 if (rc == -EBUSY)
223 pcim_pin_device(pdev);
224 if (rc)
225 return rc;
226 host->iomap = pcim_iomap_table(pdev);
227 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
228 if (rc)
229 return rc;
230 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
231 if (rc)
232 return rc;
233
234 base = host->iomap[4]; /* Bus mastering base */
235
236 for (i = 0; i < host->n_ports; i++) {
237 struct ata_port *ap = host->ports[i];
238 struct ata_ioports *ioaddr = &ap->ioaddr;
239
240 ioaddr->cmd_addr = base + offset_cmd[i];
241 ioaddr->altstatus_addr =
242 ioaddr->ctl_addr = base + offset_ctl[i];
243 ioaddr->scr_addr = NULL;
244 ata_sff_std_ports(ioaddr);
245 ioaddr->bmdma_addr = base + 8 * i;
246
247 ata_port_pbar_desc(ap, 4, -1, "ioport");
248 ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
249 }
250 pci_set_master(pdev);
251 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
252 IRQF_SHARED, &hpt3x3_sht);
253 }
254
255 #ifdef CONFIG_PM
hpt3x3_reinit_one(struct pci_dev * dev)256 static int hpt3x3_reinit_one(struct pci_dev *dev)
257 {
258 struct ata_host *host = dev_get_drvdata(&dev->dev);
259 int rc;
260
261 rc = ata_pci_device_do_resume(dev);
262 if (rc)
263 return rc;
264
265 hpt3x3_init_chipset(dev);
266
267 ata_host_resume(host);
268 return 0;
269 }
270 #endif
271
272 static const struct pci_device_id hpt3x3[] = {
273 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
274
275 { },
276 };
277
278 static struct pci_driver hpt3x3_pci_driver = {
279 .name = DRV_NAME,
280 .id_table = hpt3x3,
281 .probe = hpt3x3_init_one,
282 .remove = ata_pci_remove_one,
283 #ifdef CONFIG_PM
284 .suspend = ata_pci_device_suspend,
285 .resume = hpt3x3_reinit_one,
286 #endif
287 };
288
hpt3x3_init(void)289 static int __init hpt3x3_init(void)
290 {
291 return pci_register_driver(&hpt3x3_pci_driver);
292 }
293
294
hpt3x3_exit(void)295 static void __exit hpt3x3_exit(void)
296 {
297 pci_unregister_driver(&hpt3x3_pci_driver);
298 }
299
300
301 MODULE_AUTHOR("Alan Cox");
302 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
303 MODULE_LICENSE("GPL");
304 MODULE_DEVICE_TABLE(pci, hpt3x3);
305 MODULE_VERSION(DRV_VERSION);
306
307 module_init(hpt3x3_init);
308 module_exit(hpt3x3_exit);
309