1 /*
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 */
7
8 #ifndef _ASM_X86_DMA_H
9 #define _ASM_X86_DMA_H
10
11 #include <linux/spinlock.h> /* And spinlocks */
12 #include <asm/io.h> /* need byte IO */
13
14 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
15 #define dma_outb outb_p
16 #else
17 #define dma_outb outb
18 #endif
19
20 #define dma_inb inb
21
22 /*
23 * NOTES about DMA transfers:
24 *
25 * controller 1: channels 0-3, byte operations, ports 00-1F
26 * controller 2: channels 4-7, word operations, ports C0-DF
27 *
28 * - ALL registers are 8 bits only, regardless of transfer size
29 * - channel 4 is not used - cascades 1 into 2.
30 * - channels 0-3 are byte - addresses/counts are for physical bytes
31 * - channels 5-7 are word - addresses/counts are for physical words
32 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
33 * - transfer count loaded to registers is 1 less than actual count
34 * - controller 2 offsets are all even (2x offsets for controller 1)
35 * - page registers for 5-7 don't use data bit 0, represent 128K pages
36 * - page registers for 0-3 use bit 0, represent 64K pages
37 *
38 * DMA transfers are limited to the lower 16MB of _physical_ memory.
39 * Note that addresses loaded into registers must be _physical_ addresses,
40 * not logical addresses (which may differ if paging is active).
41 *
42 * Address mapping for channels 0-3:
43 *
44 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
45 * | ... | | ... | | ... |
46 * | ... | | ... | | ... |
47 * | ... | | ... | | ... |
48 * P7 ... P0 A7 ... A0 A7 ... A0
49 * | Page | Addr MSB | Addr LSB | (DMA registers)
50 *
51 * Address mapping for channels 5-7:
52 *
53 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
54 * | ... | \ \ ... \ \ \ ... \ \
55 * | ... | \ \ ... \ \ \ ... \ (not used)
56 * | ... | \ \ ... \ \ \ ... \
57 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
58 * | Page | Addr MSB | Addr LSB | (DMA registers)
59 *
60 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
61 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
62 * the hardware level, so odd-byte transfers aren't possible).
63 *
64 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
65 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
66 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
67 *
68 */
69
70 #define MAX_DMA_CHANNELS 8
71
72 #ifdef CONFIG_X86_32
73
74 /* The maximum address that we can perform a DMA transfer to on this platform */
75 #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x1000000)
76
77 #else
78
79 /* 16MB ISA DMA zone */
80 #define MAX_DMA_PFN ((16 * 1024 * 1024) >> PAGE_SHIFT)
81
82 /* 4GB broken PCI/AGP hardware bus master zone */
83 #define MAX_DMA32_PFN ((4UL * 1024 * 1024 * 1024) >> PAGE_SHIFT)
84
85 /* Compat define for old dma zone */
86 #define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
87
88 #endif
89
90 /* 8237 DMA controllers */
91 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
92 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
93
94 /* DMA controller registers */
95 #define DMA1_CMD_REG 0x08 /* command register (w) */
96 #define DMA1_STAT_REG 0x08 /* status register (r) */
97 #define DMA1_REQ_REG 0x09 /* request register (w) */
98 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
99 #define DMA1_MODE_REG 0x0B /* mode register (w) */
100 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
101 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
102 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
103 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
104 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
105
106 #define DMA2_CMD_REG 0xD0 /* command register (w) */
107 #define DMA2_STAT_REG 0xD0 /* status register (r) */
108 #define DMA2_REQ_REG 0xD2 /* request register (w) */
109 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
110 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
111 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
112 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
113 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
114 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
115 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
116
117 #define DMA_ADDR_0 0x00 /* DMA address registers */
118 #define DMA_ADDR_1 0x02
119 #define DMA_ADDR_2 0x04
120 #define DMA_ADDR_3 0x06
121 #define DMA_ADDR_4 0xC0
122 #define DMA_ADDR_5 0xC4
123 #define DMA_ADDR_6 0xC8
124 #define DMA_ADDR_7 0xCC
125
126 #define DMA_CNT_0 0x01 /* DMA count registers */
127 #define DMA_CNT_1 0x03
128 #define DMA_CNT_2 0x05
129 #define DMA_CNT_3 0x07
130 #define DMA_CNT_4 0xC2
131 #define DMA_CNT_5 0xC6
132 #define DMA_CNT_6 0xCA
133 #define DMA_CNT_7 0xCE
134
135 #define DMA_PAGE_0 0x87 /* DMA page registers */
136 #define DMA_PAGE_1 0x83
137 #define DMA_PAGE_2 0x81
138 #define DMA_PAGE_3 0x82
139 #define DMA_PAGE_5 0x8B
140 #define DMA_PAGE_6 0x89
141 #define DMA_PAGE_7 0x8A
142
143 /* I/O to memory, no autoinit, increment, single mode */
144 #define DMA_MODE_READ 0x44
145 /* memory to I/O, no autoinit, increment, single mode */
146 #define DMA_MODE_WRITE 0x48
147 /* pass thru DREQ->HRQ, DACK<-HLDA only */
148 #define DMA_MODE_CASCADE 0xC0
149
150 #define DMA_AUTOINIT 0x10
151
152
153 #ifdef CONFIG_ISA_DMA_API
154 extern spinlock_t dma_spin_lock;
155
claim_dma_lock(void)156 static inline unsigned long claim_dma_lock(void)
157 {
158 unsigned long flags;
159 spin_lock_irqsave(&dma_spin_lock, flags);
160 return flags;
161 }
162
release_dma_lock(unsigned long flags)163 static inline void release_dma_lock(unsigned long flags)
164 {
165 spin_unlock_irqrestore(&dma_spin_lock, flags);
166 }
167 #endif /* CONFIG_ISA_DMA_API */
168
169 /* enable/disable a specific DMA channel */
enable_dma(unsigned int dmanr)170 static inline void enable_dma(unsigned int dmanr)
171 {
172 if (dmanr <= 3)
173 dma_outb(dmanr, DMA1_MASK_REG);
174 else
175 dma_outb(dmanr & 3, DMA2_MASK_REG);
176 }
177
disable_dma(unsigned int dmanr)178 static inline void disable_dma(unsigned int dmanr)
179 {
180 if (dmanr <= 3)
181 dma_outb(dmanr | 4, DMA1_MASK_REG);
182 else
183 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
184 }
185
186 /* Clear the 'DMA Pointer Flip Flop'.
187 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
188 * Use this once to initialize the FF to a known state.
189 * After that, keep track of it. :-)
190 * --- In order to do that, the DMA routines below should ---
191 * --- only be used while holding the DMA lock ! ---
192 */
clear_dma_ff(unsigned int dmanr)193 static inline void clear_dma_ff(unsigned int dmanr)
194 {
195 if (dmanr <= 3)
196 dma_outb(0, DMA1_CLEAR_FF_REG);
197 else
198 dma_outb(0, DMA2_CLEAR_FF_REG);
199 }
200
201 /* set mode (above) for a specific DMA channel */
set_dma_mode(unsigned int dmanr,char mode)202 static inline void set_dma_mode(unsigned int dmanr, char mode)
203 {
204 if (dmanr <= 3)
205 dma_outb(mode | dmanr, DMA1_MODE_REG);
206 else
207 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
208 }
209
210 /* Set only the page register bits of the transfer address.
211 * This is used for successive transfers when we know the contents of
212 * the lower 16 bits of the DMA current address register, but a 64k boundary
213 * may have been crossed.
214 */
set_dma_page(unsigned int dmanr,char pagenr)215 static inline void set_dma_page(unsigned int dmanr, char pagenr)
216 {
217 switch (dmanr) {
218 case 0:
219 dma_outb(pagenr, DMA_PAGE_0);
220 break;
221 case 1:
222 dma_outb(pagenr, DMA_PAGE_1);
223 break;
224 case 2:
225 dma_outb(pagenr, DMA_PAGE_2);
226 break;
227 case 3:
228 dma_outb(pagenr, DMA_PAGE_3);
229 break;
230 case 5:
231 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
232 break;
233 case 6:
234 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
235 break;
236 case 7:
237 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
238 break;
239 }
240 }
241
242
243 /* Set transfer address & page bits for specific DMA channel.
244 * Assumes dma flipflop is clear.
245 */
set_dma_addr(unsigned int dmanr,unsigned int a)246 static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
247 {
248 set_dma_page(dmanr, a>>16);
249 if (dmanr <= 3) {
250 dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
251 dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
252 } else {
253 dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
254 dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
255 }
256 }
257
258
259 /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
260 * a specific DMA channel.
261 * You must ensure the parameters are valid.
262 * NOTE: from a manual: "the number of transfers is one more
263 * than the initial word count"! This is taken into account.
264 * Assumes dma flip-flop is clear.
265 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
266 */
set_dma_count(unsigned int dmanr,unsigned int count)267 static inline void set_dma_count(unsigned int dmanr, unsigned int count)
268 {
269 count--;
270 if (dmanr <= 3) {
271 dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
272 dma_outb((count >> 8) & 0xff,
273 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
274 } else {
275 dma_outb((count >> 1) & 0xff,
276 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
277 dma_outb((count >> 9) & 0xff,
278 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
279 }
280 }
281
282
283 /* Get DMA residue count. After a DMA transfer, this
284 * should return zero. Reading this while a DMA transfer is
285 * still in progress will return unpredictable results.
286 * If called before the channel has been used, it may return 1.
287 * Otherwise, it returns the number of _bytes_ left to transfer.
288 *
289 * Assumes DMA flip-flop is clear.
290 */
get_dma_residue(unsigned int dmanr)291 static inline int get_dma_residue(unsigned int dmanr)
292 {
293 unsigned int io_port;
294 /* using short to get 16-bit wrap around */
295 unsigned short count;
296
297 io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
298 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
299
300 count = 1 + dma_inb(io_port);
301 count += dma_inb(io_port) << 8;
302
303 return (dmanr <= 3) ? count : (count << 1);
304 }
305
306
307 /* These are in kernel/dma.c because x86 uses CONFIG_GENERIC_ISA_DMA */
308 #ifdef CONFIG_ISA_DMA_API
309 extern int request_dma(unsigned int dmanr, const char *device_id);
310 extern void free_dma(unsigned int dmanr);
311 #endif
312
313 /* From PCI */
314
315 #ifdef CONFIG_PCI
316 extern int isa_dma_bridge_buggy;
317 #else
318 #define isa_dma_bridge_buggy (0)
319 #endif
320
321 #endif /* _ASM_X86_DMA_H */
322