1 #ifndef __ASM_SH_IO_H
2 #define __ASM_SH_IO_H
3
4 /*
5 * Convention:
6 * read{b,w,l,q}/write{b,w,l,q} are for PCI,
7 * while in{b,w,l}/out{b,w,l} are for ISA
8 *
9 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
10 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
11 *
12 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
13 * automatically, there are also __raw versions, which do not.
14 */
15 #include <linux/errno.h>
16 #include <asm/cache.h>
17 #include <asm/system.h>
18 #include <asm/addrspace.h>
19 #include <asm/machvec.h>
20 #include <asm/pgtable.h>
21 #include <asm-generic/iomap.h>
22
23 #ifdef __KERNEL__
24 #define __IO_PREFIX generic
25 #include <asm/io_generic.h>
26 #include <asm/io_trapped.h>
27
28 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
29 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
30 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
31 #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
32
33 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
34 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
35 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
36 #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
37
38 #define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
39 #define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
40 __raw_readw(c)); __v; })
41 #define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \
42 __raw_readl(c)); __v; })
43 #define readq_relaxed(c) ({ u64 __v = le64_to_cpu((__force __le64) \
44 __raw_readq(c)); __v; })
45
46 #define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
47 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
48 cpu_to_le16(v),c))
49 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
50 cpu_to_le32(v),c))
51 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64) \
52 cpu_to_le64(v),c))
53
54 #define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
55 #define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
56 #define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
57 #define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
58
59 #define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
60 #define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
61 #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
62 #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
63
64 #define readsb(p,d,l) __raw_readsb(p,d,l)
65 #define readsw(p,d,l) __raw_readsw(p,d,l)
66 #define readsl(p,d,l) __raw_readsl(p,d,l)
67
68 #define writesb(p,d,l) __raw_writesb(p,d,l)
69 #define writesw(p,d,l) __raw_writesw(p,d,l)
70 #define writesl(p,d,l) __raw_writesl(p,d,l)
71
72 #define __BUILD_UNCACHED_IO(bwlq, type) \
73 static inline type read##bwlq##_uncached(unsigned long addr) \
74 { \
75 type ret; \
76 jump_to_uncached(); \
77 ret = __raw_read##bwlq(addr); \
78 back_to_cached(); \
79 return ret; \
80 } \
81 \
82 static inline void write##bwlq##_uncached(type v, unsigned long addr) \
83 { \
84 jump_to_uncached(); \
85 __raw_write##bwlq(v, addr); \
86 back_to_cached(); \
87 }
88
89 __BUILD_UNCACHED_IO(b, u8)
90 __BUILD_UNCACHED_IO(w, u16)
91 __BUILD_UNCACHED_IO(l, u32)
92 __BUILD_UNCACHED_IO(q, u64)
93
94 #define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
95 \
96 static inline void \
97 pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
98 unsigned int count) \
99 { \
100 const volatile type *__addr = addr; \
101 \
102 while (count--) { \
103 __raw_write##bwlq(*__addr, mem); \
104 __addr++; \
105 } \
106 } \
107 \
108 static inline void pfx##reads##bwlq(volatile void __iomem *mem, \
109 void *addr, unsigned int count) \
110 { \
111 volatile type *__addr = addr; \
112 \
113 while (count--) { \
114 *__addr = __raw_read##bwlq(mem); \
115 __addr++; \
116 } \
117 }
118
119 __BUILD_MEMORY_STRING(__raw_, b, u8)
120 __BUILD_MEMORY_STRING(__raw_, w, u16)
121
122 #ifdef CONFIG_SUPERH32
123 void __raw_writesl(void __iomem *addr, const void *data, int longlen);
124 void __raw_readsl(const void __iomem *addr, void *data, int longlen);
125 #else
126 __BUILD_MEMORY_STRING(__raw_, l, u32)
127 #endif
128
129 __BUILD_MEMORY_STRING(__raw_, q, u64)
130
131 #ifdef CONFIG_HAS_IOPORT
132
133 /*
134 * Slowdown I/O port space accesses for antique hardware.
135 */
136 #undef CONF_SLOWDOWN_IO
137
138 /*
139 * On SuperH I/O ports are memory mapped, so we access them using normal
140 * load/store instructions. sh_io_port_base is the virtual address to
141 * which all ports are being mapped.
142 */
143 extern const unsigned long sh_io_port_base;
144
__set_io_port_base(unsigned long pbase)145 static inline void __set_io_port_base(unsigned long pbase)
146 {
147 *(unsigned long *)&sh_io_port_base = pbase;
148 barrier();
149 }
150
151 #ifdef CONFIG_GENERIC_IOMAP
152 #define __ioport_map ioport_map
153 #else
154 extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
155 #endif
156
157 #ifdef CONF_SLOWDOWN_IO
158 #define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
159 #else
160 #define SLOW_DOWN_IO
161 #endif
162
163 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
164 \
165 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
166 { \
167 volatile type *__addr; \
168 \
169 __addr = __ioport_map(port, sizeof(type)); \
170 *__addr = val; \
171 slow; \
172 } \
173 \
174 static inline type pfx##in##bwlq##p(unsigned long port) \
175 { \
176 volatile type *__addr; \
177 type __val; \
178 \
179 __addr = __ioport_map(port, sizeof(type)); \
180 __val = *__addr; \
181 slow; \
182 \
183 return __val; \
184 }
185
186 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
187 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
188 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
189
190 #define BUILDIO_IOPORT(bwlq, type) \
191 __BUILD_IOPORT_PFX(, bwlq, type)
192
193 BUILDIO_IOPORT(b, u8)
194 BUILDIO_IOPORT(w, u16)
195 BUILDIO_IOPORT(l, u32)
196 BUILDIO_IOPORT(q, u64)
197
198 #define __BUILD_IOPORT_STRING(bwlq, type) \
199 \
200 static inline void outs##bwlq(unsigned long port, const void *addr, \
201 unsigned int count) \
202 { \
203 const volatile type *__addr = addr; \
204 \
205 while (count--) { \
206 out##bwlq(*__addr, port); \
207 __addr++; \
208 } \
209 } \
210 \
211 static inline void ins##bwlq(unsigned long port, void *addr, \
212 unsigned int count) \
213 { \
214 volatile type *__addr = addr; \
215 \
216 while (count--) { \
217 *__addr = in##bwlq(port); \
218 __addr++; \
219 } \
220 }
221
222 __BUILD_IOPORT_STRING(b, u8)
223 __BUILD_IOPORT_STRING(w, u16)
224 __BUILD_IOPORT_STRING(l, u32)
225 __BUILD_IOPORT_STRING(q, u64)
226
227 #endif
228
229 #define IO_SPACE_LIMIT 0xffffffff
230
231 /* synco on SH-4A, otherwise a nop */
232 #define mmiowb() wmb()
233
234 /* We really want to try and get these to memcpy etc */
235 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
236 void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
237 void memset_io(volatile void __iomem *, int, unsigned long);
238
239 /* Quad-word real-mode I/O, don't ask.. */
240 unsigned long long peek_real_address_q(unsigned long long addr);
241 unsigned long long poke_real_address_q(unsigned long long addr,
242 unsigned long long val);
243
244 #if !defined(CONFIG_MMU)
245 #define virt_to_phys(address) ((unsigned long)(address))
246 #define phys_to_virt(address) ((void *)(address))
247 #else
248 #define virt_to_phys(address) (__pa(address))
249 #define phys_to_virt(address) (__va(address))
250 #endif
251
252 /*
253 * On 32-bit SH, we traditionally have the whole physical address space
254 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
255 * not need to do anything but place the address in the proper segment.
256 * This is true for P1 and P2 addresses, as well as some P3 ones.
257 * However, most of the P3 addresses and newer cores using extended
258 * addressing need to map through page tables, so the ioremap()
259 * implementation becomes a bit more complicated.
260 *
261 * See arch/sh/mm/ioremap.c for additional notes on this.
262 *
263 * We cheat a bit and always return uncachable areas until we've fixed
264 * the drivers to handle caching properly.
265 *
266 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
267 * doesn't exist, so everything must go through page tables.
268 */
269 #ifdef CONFIG_MMU
270 void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
271 pgprot_t prot, void *caller);
272 void __iounmap(void __iomem *addr);
273
274 static inline void __iomem *
__ioremap(phys_addr_t offset,unsigned long size,pgprot_t prot)275 __ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
276 {
277 return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
278 }
279
280 static inline void __iomem *
__ioremap_29bit(phys_addr_t offset,unsigned long size,pgprot_t prot)281 __ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
282 {
283 #ifdef CONFIG_29BIT
284 phys_addr_t last_addr = offset + size - 1;
285
286 /*
287 * For P1 and P2 space this is trivial, as everything is already
288 * mapped. Uncached access for P1 addresses are done through P2.
289 * In the P3 case or for addresses outside of the 29-bit space,
290 * mapping must be done by the PMB or by using page tables.
291 */
292 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
293 u64 flags = pgprot_val(prot);
294
295 /*
296 * Anything using the legacy PTEA space attributes needs
297 * to be kicked down to page table mappings.
298 */
299 if (unlikely(flags & _PAGE_PCC_MASK))
300 return NULL;
301 if (unlikely(flags & _PAGE_CACHABLE))
302 return (void __iomem *)P1SEGADDR(offset);
303
304 return (void __iomem *)P2SEGADDR(offset);
305 }
306
307 /* P4 above the store queues are always mapped. */
308 if (unlikely(offset >= P3_ADDR_MAX))
309 return (void __iomem *)P4SEGADDR(offset);
310 #endif
311
312 return NULL;
313 }
314
315 static inline void __iomem *
__ioremap_mode(phys_addr_t offset,unsigned long size,pgprot_t prot)316 __ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
317 {
318 void __iomem *ret;
319
320 ret = __ioremap_trapped(offset, size);
321 if (ret)
322 return ret;
323
324 ret = __ioremap_29bit(offset, size, prot);
325 if (ret)
326 return ret;
327
328 return __ioremap(offset, size, prot);
329 }
330 #else
331 #define __ioremap(offset, size, prot) ((void __iomem *)(offset))
332 #define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset))
333 #define __iounmap(addr) do { } while (0)
334 #endif /* CONFIG_MMU */
335
ioremap(phys_addr_t offset,unsigned long size)336 static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
337 {
338 return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
339 }
340
341 static inline void __iomem *
ioremap_cache(phys_addr_t offset,unsigned long size)342 ioremap_cache(phys_addr_t offset, unsigned long size)
343 {
344 return __ioremap_mode(offset, size, PAGE_KERNEL);
345 }
346
347 #ifdef CONFIG_HAVE_IOREMAP_PROT
348 static inline void __iomem *
ioremap_prot(phys_addr_t offset,unsigned long size,unsigned long flags)349 ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
350 {
351 return __ioremap_mode(offset, size, __pgprot(flags));
352 }
353 #endif
354
355 #ifdef CONFIG_IOREMAP_FIXED
356 extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
357 extern int iounmap_fixed(void __iomem *);
358 extern void ioremap_fixed_init(void);
359 #else
360 static inline void __iomem *
ioremap_fixed(phys_addr_t phys_addr,unsigned long size,pgprot_t prot)361 ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
362 {
363 BUG();
364 return NULL;
365 }
366
ioremap_fixed_init(void)367 static inline void ioremap_fixed_init(void) { }
iounmap_fixed(void __iomem * addr)368 static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
369 #endif
370
371 #define ioremap_nocache ioremap
372 #define iounmap __iounmap
373
374 /*
375 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
376 * access
377 */
378 #define xlate_dev_mem_ptr(p) __va(p)
379
380 /*
381 * Convert a virtual cached pointer to an uncached pointer
382 */
383 #define xlate_dev_kmem_ptr(p) p
384
385 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
386 int valid_phys_addr_range(unsigned long addr, size_t size);
387 int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
388
389 #endif /* __KERNEL__ */
390
391 #endif /* __ASM_SH_IO_H */
392