1config PPC_CELL
2	bool
3	default n
4
5config PPC_CELL_COMMON
6	bool
7	select PPC_CELL
8	select PPC_DCR_MMIO
9	select PPC_INDIRECT_IO
10	select PPC_NATIVE
11	select PPC_RTAS
12	select IRQ_EDGE_EOI_HANDLER
13
14config PPC_CELL_NATIVE
15	bool
16	select PPC_CELL_COMMON
17	select MPIC
18	select IBM_NEW_EMAC_EMAC4
19	select IBM_NEW_EMAC_RGMII
20	select IBM_NEW_EMAC_ZMII #test only
21	select IBM_NEW_EMAC_TAH  #test only
22	default n
23
24config PPC_IBM_CELL_BLADE
25	bool "IBM Cell Blade"
26	depends on PPC64 && PPC_BOOK3S
27	select PPC_CELL_NATIVE
28	select PPC_OF_PLATFORM_PCI
29	select PCI
30	select MMIO_NVRAM
31	select PPC_UDBG_16550
32	select UDBG_RTAS_CONSOLE
33
34config PPC_CELLEB
35	bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
36	depends on PPC64 && PPC_BOOK3S
37	select PPC_CELL_NATIVE
38	select PPC_OF_PLATFORM_PCI
39	select PCI
40	select HAS_TXX9_SERIAL
41	select PPC_UDBG_BEAT
42	select USB_OHCI_BIG_ENDIAN_MMIO
43	select USB_EHCI_BIG_ENDIAN_MMIO
44
45config PPC_CELL_QPACE
46	bool "IBM Cell - QPACE"
47	depends on PPC64 && PPC_BOOK3S
48	select PPC_CELL_COMMON
49
50config AXON_MSI
51	bool
52	depends on PPC_IBM_CELL_BLADE && PCI_MSI
53	default y
54
55menu "Cell Broadband Engine options"
56	depends on PPC_CELL
57
58config SPU_FS
59	tristate "SPU file system"
60	default m
61	depends on PPC_CELL
62	select SPU_BASE
63	select MEMORY_HOTPLUG
64	help
65	  The SPU file system is used to access Synergistic Processing
66	  Units on machines implementing the Broadband Processor
67	  Architecture.
68
69config SPU_FS_64K_LS
70	bool "Use 64K pages to map SPE local  store"
71	# we depend on PPC_MM_SLICES for now rather than selecting
72	# it because we depend on hugetlbfs hooks being present. We
73	# will fix that when the generic code has been improved to
74	# not require hijacking hugetlbfs hooks.
75	depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
76	default y
77	select PPC_HAS_HASH_64K
78	help
79	  This option causes SPE local stores to be mapped in process
80	  address spaces using 64K pages while the rest of the kernel
81	  uses 4K pages. This can improve performances of applications
82	  using multiple SPEs by lowering the TLB pressure on them.
83
84config SPU_BASE
85	bool
86	default n
87
88config CBE_RAS
89	bool "RAS features for bare metal Cell BE"
90	depends on PPC_CELL_NATIVE
91	default y
92
93config PPC_IBM_CELL_RESETBUTTON
94	bool "IBM Cell Blade Pinhole reset button"
95	depends on CBE_RAS && PPC_IBM_CELL_BLADE
96	default y
97	help
98	  Support Pinhole Resetbutton on IBM Cell blades.
99	  This adds a method to trigger system reset via front panel pinhole button.
100
101config PPC_IBM_CELL_POWERBUTTON
102	tristate "IBM Cell Blade power button"
103	depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
104	default y
105	help
106	  Support Powerbutton on IBM Cell blades.
107	  This will enable the powerbutton as an input device.
108
109config CBE_THERM
110	tristate "CBE thermal support"
111	default m
112	depends on CBE_RAS && SPU_BASE
113
114config CBE_CPUFREQ
115	tristate "CBE frequency scaling"
116	depends on CBE_RAS && CPU_FREQ
117	default m
118	help
119	  This adds the cpufreq driver for Cell BE processors.
120	  For details, take a look at <file:Documentation/cpu-freq/>.
121	  If you don't have such processor, say N
122
123config CBE_CPUFREQ_PMI_ENABLE
124	bool "CBE frequency scaling using PMI interface"
125	depends on CBE_CPUFREQ && EXPERIMENTAL
126	default n
127	help
128	  Select this, if you want to use the PMI interface
129	  to switch frequencies. Using PMI, the
130	  processor will not only be able to run at lower speed,
131	  but also at lower core voltage.
132
133config CBE_CPUFREQ_PMI
134	tristate
135	depends on CBE_CPUFREQ_PMI_ENABLE
136	default CBE_CPUFREQ
137
138config PPC_PMI
139	tristate
140	default y
141	depends on CBE_CPUFREQ_PMI || PPC_IBM_CELL_POWERBUTTON
142	help
143	  PMI (Platform Management Interrupt) is a way to
144	  communicate with the BMC (Baseboard Management Controller).
145	  It is used in some IBM Cell blades.
146
147config CBE_CPUFREQ_SPU_GOVERNOR
148	tristate "CBE frequency scaling based on SPU usage"
149	depends on SPU_FS && CPU_FREQ
150	default m
151	help
152	  This governor checks for spu usage to adjust the cpu frequency.
153	  If no spu is running on a given cpu, that cpu will be throttled to
154	  the minimal possible frequency.
155
156endmenu
157
158config OPROFILE_CELL
159	def_bool y
160	depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE
161
162