1/*
2 * MPC832x RDB Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "MPC8323ERDB";
16	compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet1;
22		ethernet1 = &enet0;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,8323@0 {
33			device_type = "cpu";
34			reg = <0x0>;
35			d-cache-line-size = <0x20>;	// 32 bytes
36			i-cache-line-size = <0x20>;	// 32 bytes
37			d-cache-size = <16384>;	// L1, 16K
38			i-cache-size = <16384>;	// L1, 16K
39			timebase-frequency = <0>;
40			bus-frequency = <0>;
41			clock-frequency = <0>;
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x04000000>;
48	};
49
50	soc8323@e0000000 {
51		#address-cells = <1>;
52		#size-cells = <1>;
53		device_type = "soc";
54		compatible = "simple-bus";
55		ranges = <0x0 0xe0000000 0x00100000>;
56		reg = <0xe0000000 0x00000200>;
57		bus-frequency = <0>;
58
59		wdt@200 {
60			device_type = "watchdog";
61			compatible = "mpc83xx_wdt";
62			reg = <0x200 0x100>;
63		};
64
65		pmc: power@b00 {
66			compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
67			reg = <0xb00 0x100 0xa00 0x100>;
68			interrupts = <80 0x8>;
69			interrupt-parent = <&ipic>;
70		};
71
72		i2c@3000 {
73			#address-cells = <1>;
74			#size-cells = <0>;
75			cell-index = <0>;
76			compatible = "fsl-i2c";
77			reg = <0x3000 0x100>;
78			interrupts = <14 0x8>;
79			interrupt-parent = <&ipic>;
80			dfsrr;
81		};
82
83		serial0: serial@4500 {
84			cell-index = <0>;
85			device_type = "serial";
86			compatible = "ns16550";
87			reg = <0x4500 0x100>;
88			clock-frequency = <0>;
89			interrupts = <9 0x8>;
90			interrupt-parent = <&ipic>;
91		};
92
93		serial1: serial@4600 {
94			cell-index = <1>;
95			device_type = "serial";
96			compatible = "ns16550";
97			reg = <0x4600 0x100>;
98			clock-frequency = <0>;
99			interrupts = <10 0x8>;
100			interrupt-parent = <&ipic>;
101		};
102
103		dma@82a8 {
104			#address-cells = <1>;
105			#size-cells = <1>;
106			compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
107			reg = <0x82a8 4>;
108			ranges = <0 0x8100 0x1a8>;
109			interrupt-parent = <&ipic>;
110			interrupts = <71 8>;
111			cell-index = <0>;
112			dma-channel@0 {
113				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
114				reg = <0 0x80>;
115				cell-index = <0>;
116				interrupt-parent = <&ipic>;
117				interrupts = <71 8>;
118			};
119			dma-channel@80 {
120				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
121				reg = <0x80 0x80>;
122				cell-index = <1>;
123				interrupt-parent = <&ipic>;
124				interrupts = <71 8>;
125			};
126			dma-channel@100 {
127				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
128				reg = <0x100 0x80>;
129				cell-index = <2>;
130				interrupt-parent = <&ipic>;
131				interrupts = <71 8>;
132			};
133			dma-channel@180 {
134				compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
135				reg = <0x180 0x28>;
136				cell-index = <3>;
137				interrupt-parent = <&ipic>;
138				interrupts = <71 8>;
139			};
140		};
141
142		crypto@30000 {
143			compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
144			reg = <0x30000 0x10000>;
145			interrupts = <11 0x8>;
146			interrupt-parent = <&ipic>;
147			fsl,num-channels = <1>;
148			fsl,channel-fifo-len = <24>;
149			fsl,exec-units-mask = <0x4c>;
150			fsl,descriptor-types-mask = <0x0122003f>;
151			sleep = <&pmc 0x03000000>;
152		};
153
154		ipic:pic@700 {
155			interrupt-controller;
156			#address-cells = <0>;
157			#interrupt-cells = <2>;
158			reg = <0x700 0x100>;
159			device_type = "ipic";
160		};
161
162		par_io@1400 {
163			#address-cells = <1>;
164			#size-cells = <1>;
165			reg = <0x1400 0x100>;
166			ranges = <3 0x1448 0x18>;
167			compatible = "fsl,mpc8323-qe-pario";
168			device_type = "par_io";
169			num-ports = <7>;
170
171			qe_pio_d: gpio-controller@1448 {
172				#gpio-cells = <2>;
173				compatible = "fsl,mpc8323-qe-pario-bank";
174				reg = <3 0x18>;
175				gpio-controller;
176			};
177
178			ucc2pio:ucc_pin@02 {
179				pio-map = <
180			/* port  pin  dir  open_drain  assignment  has_irq */
181					3  4  3  0  2  0 	/* MDIO */
182					3  5  1  0  2  0 	/* MDC */
183					3 21  2  0  1  0 	/* RX_CLK (CLK16) */
184					3 23  2  0  1  0 	/* TX_CLK (CLK3) */
185					0 18  1  0  1  0 	/* TxD0 */
186					0 19  1  0  1  0 	/* TxD1 */
187					0 20  1  0  1  0 	/* TxD2 */
188					0 21  1  0  1  0 	/* TxD3 */
189					0 22  2  0  1  0 	/* RxD0 */
190					0 23  2  0  1  0 	/* RxD1 */
191					0 24  2  0  1  0 	/* RxD2 */
192					0 25  2  0  1  0 	/* RxD3 */
193					0 26  2  0  1  0 	/* RX_ER */
194					0 27  1  0  1  0 	/* TX_ER */
195					0 28  2  0  1  0 	/* RX_DV */
196					0 29  2  0  1  0 	/* COL */
197					0 30  1  0  1  0 	/* TX_EN */
198					0 31  2  0  1  0>;      /* CRS */
199			};
200			ucc3pio:ucc_pin@03 {
201				pio-map = <
202			/* port  pin  dir  open_drain  assignment  has_irq */
203					0 13  2  0  1  0 	/* RX_CLK (CLK9) */
204					3 24  2  0  1  0 	/* TX_CLK (CLK10) */
205					1  0  1  0  1  0 	/* TxD0 */
206					1  1  1  0  1  0 	/* TxD1 */
207					1  2  1  0  1  0 	/* TxD2 */
208					1  3  1  0  1  0 	/* TxD3 */
209					1  4  2  0  1  0 	/* RxD0 */
210					1  5  2  0  1  0 	/* RxD1 */
211					1  6  2  0  1  0 	/* RxD2 */
212					1  7  2  0  1  0 	/* RxD3 */
213					1  8  2  0  1  0 	/* RX_ER */
214					1  9  1  0  1  0 	/* TX_ER */
215					1 10  2  0  1  0 	/* RX_DV */
216					1 11  2  0  1  0 	/* COL */
217					1 12  1  0  1  0 	/* TX_EN */
218					1 13  2  0  1  0>;      /* CRS */
219			};
220		};
221	};
222
223	qe@e0100000 {
224		#address-cells = <1>;
225		#size-cells = <1>;
226		device_type = "qe";
227		compatible = "fsl,qe";
228		ranges = <0x0 0xe0100000 0x00100000>;
229		reg = <0xe0100000 0x480>;
230		brg-frequency = <0>;
231		bus-frequency = <198000000>;
232		fsl,qe-num-riscs = <1>;
233		fsl,qe-num-snums = <28>;
234
235		muram@10000 {
236 			#address-cells = <1>;
237 			#size-cells = <1>;
238			compatible = "fsl,qe-muram", "fsl,cpm-muram";
239			ranges = <0x0 0x00010000 0x00004000>;
240
241			data-only@0 {
242				compatible = "fsl,qe-muram-data",
243					     "fsl,cpm-muram-data";
244				reg = <0x0 0x4000>;
245			};
246		};
247
248		spi@4c0 {
249			#address-cells = <1>;
250			#size-cells = <0>;
251			cell-index = <0>;
252			compatible = "fsl,spi";
253			reg = <0x4c0 0x40>;
254			interrupts = <2>;
255			interrupt-parent = <&qeic>;
256			gpios = <&qe_pio_d 13 0>;
257			mode = "cpu-qe";
258
259			mmc-slot@0 {
260				compatible = "fsl,mpc8323rdb-mmc-slot",
261					     "mmc-spi-slot";
262				reg = <0>;
263				gpios = <&qe_pio_d 14 1
264					 &qe_pio_d 15 0>;
265				voltage-ranges = <3300 3300>;
266				spi-max-frequency = <50000000>;
267			};
268		};
269
270		spi@500 {
271			cell-index = <1>;
272			compatible = "fsl,spi";
273			reg = <0x500 0x40>;
274			interrupts = <1>;
275			interrupt-parent = <&qeic>;
276			mode = "cpu";
277		};
278
279		enet0: ucc@3000 {
280			device_type = "network";
281			compatible = "ucc_geth";
282			cell-index = <2>;
283			reg = <0x3000 0x200>;
284			interrupts = <33>;
285			interrupt-parent = <&qeic>;
286			local-mac-address = [ 00 00 00 00 00 00 ];
287			rx-clock-name = "clk16";
288			tx-clock-name = "clk3";
289			phy-handle = <&phy00>;
290			pio-handle = <&ucc2pio>;
291		};
292
293		enet1: ucc@2200 {
294			device_type = "network";
295			compatible = "ucc_geth";
296			cell-index = <3>;
297			reg = <0x2200 0x200>;
298			interrupts = <34>;
299			interrupt-parent = <&qeic>;
300			local-mac-address = [ 00 00 00 00 00 00 ];
301			rx-clock-name = "clk9";
302			tx-clock-name = "clk10";
303			phy-handle = <&phy04>;
304			pio-handle = <&ucc3pio>;
305		};
306
307		mdio@3120 {
308			#address-cells = <1>;
309			#size-cells = <0>;
310			reg = <0x3120 0x18>;
311			compatible = "fsl,ucc-mdio";
312
313			phy00:ethernet-phy@00 {
314				interrupt-parent = <&ipic>;
315				interrupts = <0>;
316				reg = <0x0>;
317				device_type = "ethernet-phy";
318			};
319			phy04:ethernet-phy@04 {
320				interrupt-parent = <&ipic>;
321				interrupts = <0>;
322				reg = <0x4>;
323				device_type = "ethernet-phy";
324			};
325		};
326
327		qeic:interrupt-controller@80 {
328			interrupt-controller;
329			compatible = "fsl,qe-ic";
330			#address-cells = <0>;
331			#interrupt-cells = <1>;
332			reg = <0x80 0x80>;
333			big-endian;
334			interrupts = <32 0x8 33 0x8>; //high:32 low:33
335			interrupt-parent = <&ipic>;
336		};
337	};
338
339	pci0: pci@e0008500 {
340		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
341		interrupt-map = <
342				/* IDSEL 0x10 AD16 (USB) */
343				 0x8000 0x0 0x0 0x1 &ipic 17 0x8
344
345				/* IDSEL 0x11 AD17 (Mini1)*/
346				 0x8800 0x0 0x0 0x1 &ipic 18 0x8
347				 0x8800 0x0 0x0 0x2 &ipic 19 0x8
348				 0x8800 0x0 0x0 0x3 &ipic 20 0x8
349				 0x8800 0x0 0x0 0x4 &ipic 48 0x8
350
351				/* IDSEL 0x12 AD18 (PCI/Mini2) */
352				 0x9000 0x0 0x0 0x1 &ipic 19 0x8
353				 0x9000 0x0 0x0 0x2 &ipic 20 0x8
354				 0x9000 0x0 0x0 0x3 &ipic 48 0x8
355				 0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
356
357		interrupt-parent = <&ipic>;
358		interrupts = <66 0x8>;
359		bus-range = <0x0 0x0>;
360		ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
361			  0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
362			  0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
363		clock-frequency = <0>;
364		#interrupt-cells = <1>;
365		#size-cells = <2>;
366		#address-cells = <3>;
367		reg = <0xe0008500 0x100		/* internal registers */
368		       0xe0008300 0x8>;		/* config space access registers */
369		compatible = "fsl,mpc8349-pci";
370		device_type = "pci";
371		sleep = <&pmc 0x00010000>;
372	};
373};
374