1 /*
2 * pci.c: GT64120 PCI support.
3 *
4 * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/init.h>
11 #include <linux/ioport.h>
12 #include <linux/types.h>
13 #include <linux/pci.h>
14
15 #include <asm/gt64120.h>
16
17 extern struct pci_ops gt64xxx_pci0_ops;
18
19 static struct resource pci0_io_resource = {
20 .name = "pci_0 io",
21 .start = GT_PCI_IO_BASE,
22 .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
23 .flags = IORESOURCE_IO,
24 };
25
26 static struct resource pci0_mem_resource = {
27 .name = "pci_0 memory",
28 .start = GT_PCI_MEM_BASE,
29 .end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1,
30 .flags = IORESOURCE_MEM,
31 };
32
33 static struct pci_controller hose_0 = {
34 .pci_ops = >64xxx_pci0_ops,
35 .io_resource = &pci0_io_resource,
36 .mem_resource = &pci0_mem_resource,
37 };
38
gt64120_pci_init(void)39 static int __init gt64120_pci_init(void)
40 {
41 u32 tmp;
42
43 tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */
44 tmp = GT_READ(GT_PCI0_BARE_OFS);
45
46 /* reset the whole PCI I/O space range */
47 ioport_resource.start = GT_PCI_IO_BASE;
48 ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
49
50 register_pci_controller(&hose_0);
51 return 0;
52 }
53
54 arch_initcall(gt64120_pci_init);
55