1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2010 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_MIXX_DEFS_H__ 29 #define __CVMX_MIXX_DEFS_H__ 30 31 #define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048) 32 #define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048) 33 #define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048) 34 #define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048) 35 #define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048) 36 #define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048) 37 #define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048) 38 #define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048) 39 #define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048) 40 #define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048) 41 #define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048) 42 #define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048) 43 #define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048) 44 #define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048) 45 #define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048) 46 47 union cvmx_mixx_bist { 48 uint64_t u64; 49 struct cvmx_mixx_bist_s { 50 uint64_t reserved_6_63:58; 51 uint64_t opfdat:1; 52 uint64_t mrgdat:1; 53 uint64_t mrqdat:1; 54 uint64_t ipfdat:1; 55 uint64_t irfdat:1; 56 uint64_t orfdat:1; 57 } s; 58 struct cvmx_mixx_bist_cn52xx { 59 uint64_t reserved_4_63:60; 60 uint64_t mrqdat:1; 61 uint64_t ipfdat:1; 62 uint64_t irfdat:1; 63 uint64_t orfdat:1; 64 } cn52xx; 65 struct cvmx_mixx_bist_cn52xx cn52xxp1; 66 struct cvmx_mixx_bist_cn52xx cn56xx; 67 struct cvmx_mixx_bist_cn52xx cn56xxp1; 68 struct cvmx_mixx_bist_s cn63xx; 69 struct cvmx_mixx_bist_s cn63xxp1; 70 }; 71 72 union cvmx_mixx_ctl { 73 uint64_t u64; 74 struct cvmx_mixx_ctl_s { 75 uint64_t reserved_12_63:52; 76 uint64_t ts_thresh:4; 77 uint64_t crc_strip:1; 78 uint64_t busy:1; 79 uint64_t en:1; 80 uint64_t reset:1; 81 uint64_t lendian:1; 82 uint64_t nbtarb:1; 83 uint64_t mrq_hwm:2; 84 } s; 85 struct cvmx_mixx_ctl_cn52xx { 86 uint64_t reserved_8_63:56; 87 uint64_t crc_strip:1; 88 uint64_t busy:1; 89 uint64_t en:1; 90 uint64_t reset:1; 91 uint64_t lendian:1; 92 uint64_t nbtarb:1; 93 uint64_t mrq_hwm:2; 94 } cn52xx; 95 struct cvmx_mixx_ctl_cn52xx cn52xxp1; 96 struct cvmx_mixx_ctl_cn52xx cn56xx; 97 struct cvmx_mixx_ctl_cn52xx cn56xxp1; 98 struct cvmx_mixx_ctl_s cn63xx; 99 struct cvmx_mixx_ctl_s cn63xxp1; 100 }; 101 102 union cvmx_mixx_intena { 103 uint64_t u64; 104 struct cvmx_mixx_intena_s { 105 uint64_t reserved_8_63:56; 106 uint64_t tsena:1; 107 uint64_t orunena:1; 108 uint64_t irunena:1; 109 uint64_t data_drpena:1; 110 uint64_t ithena:1; 111 uint64_t othena:1; 112 uint64_t ivfena:1; 113 uint64_t ovfena:1; 114 } s; 115 struct cvmx_mixx_intena_cn52xx { 116 uint64_t reserved_7_63:57; 117 uint64_t orunena:1; 118 uint64_t irunena:1; 119 uint64_t data_drpena:1; 120 uint64_t ithena:1; 121 uint64_t othena:1; 122 uint64_t ivfena:1; 123 uint64_t ovfena:1; 124 } cn52xx; 125 struct cvmx_mixx_intena_cn52xx cn52xxp1; 126 struct cvmx_mixx_intena_cn52xx cn56xx; 127 struct cvmx_mixx_intena_cn52xx cn56xxp1; 128 struct cvmx_mixx_intena_s cn63xx; 129 struct cvmx_mixx_intena_s cn63xxp1; 130 }; 131 132 union cvmx_mixx_ircnt { 133 uint64_t u64; 134 struct cvmx_mixx_ircnt_s { 135 uint64_t reserved_20_63:44; 136 uint64_t ircnt:20; 137 } s; 138 struct cvmx_mixx_ircnt_s cn52xx; 139 struct cvmx_mixx_ircnt_s cn52xxp1; 140 struct cvmx_mixx_ircnt_s cn56xx; 141 struct cvmx_mixx_ircnt_s cn56xxp1; 142 struct cvmx_mixx_ircnt_s cn63xx; 143 struct cvmx_mixx_ircnt_s cn63xxp1; 144 }; 145 146 union cvmx_mixx_irhwm { 147 uint64_t u64; 148 struct cvmx_mixx_irhwm_s { 149 uint64_t reserved_40_63:24; 150 uint64_t ibplwm:20; 151 uint64_t irhwm:20; 152 } s; 153 struct cvmx_mixx_irhwm_s cn52xx; 154 struct cvmx_mixx_irhwm_s cn52xxp1; 155 struct cvmx_mixx_irhwm_s cn56xx; 156 struct cvmx_mixx_irhwm_s cn56xxp1; 157 struct cvmx_mixx_irhwm_s cn63xx; 158 struct cvmx_mixx_irhwm_s cn63xxp1; 159 }; 160 161 union cvmx_mixx_iring1 { 162 uint64_t u64; 163 struct cvmx_mixx_iring1_s { 164 uint64_t reserved_60_63:4; 165 uint64_t isize:20; 166 uint64_t ibase:37; 167 uint64_t reserved_0_2:3; 168 } s; 169 struct cvmx_mixx_iring1_cn52xx { 170 uint64_t reserved_60_63:4; 171 uint64_t isize:20; 172 uint64_t reserved_36_39:4; 173 uint64_t ibase:33; 174 uint64_t reserved_0_2:3; 175 } cn52xx; 176 struct cvmx_mixx_iring1_cn52xx cn52xxp1; 177 struct cvmx_mixx_iring1_cn52xx cn56xx; 178 struct cvmx_mixx_iring1_cn52xx cn56xxp1; 179 struct cvmx_mixx_iring1_s cn63xx; 180 struct cvmx_mixx_iring1_s cn63xxp1; 181 }; 182 183 union cvmx_mixx_iring2 { 184 uint64_t u64; 185 struct cvmx_mixx_iring2_s { 186 uint64_t reserved_52_63:12; 187 uint64_t itlptr:20; 188 uint64_t reserved_20_31:12; 189 uint64_t idbell:20; 190 } s; 191 struct cvmx_mixx_iring2_s cn52xx; 192 struct cvmx_mixx_iring2_s cn52xxp1; 193 struct cvmx_mixx_iring2_s cn56xx; 194 struct cvmx_mixx_iring2_s cn56xxp1; 195 struct cvmx_mixx_iring2_s cn63xx; 196 struct cvmx_mixx_iring2_s cn63xxp1; 197 }; 198 199 union cvmx_mixx_isr { 200 uint64_t u64; 201 struct cvmx_mixx_isr_s { 202 uint64_t reserved_8_63:56; 203 uint64_t ts:1; 204 uint64_t orun:1; 205 uint64_t irun:1; 206 uint64_t data_drp:1; 207 uint64_t irthresh:1; 208 uint64_t orthresh:1; 209 uint64_t idblovf:1; 210 uint64_t odblovf:1; 211 } s; 212 struct cvmx_mixx_isr_cn52xx { 213 uint64_t reserved_7_63:57; 214 uint64_t orun:1; 215 uint64_t irun:1; 216 uint64_t data_drp:1; 217 uint64_t irthresh:1; 218 uint64_t orthresh:1; 219 uint64_t idblovf:1; 220 uint64_t odblovf:1; 221 } cn52xx; 222 struct cvmx_mixx_isr_cn52xx cn52xxp1; 223 struct cvmx_mixx_isr_cn52xx cn56xx; 224 struct cvmx_mixx_isr_cn52xx cn56xxp1; 225 struct cvmx_mixx_isr_s cn63xx; 226 struct cvmx_mixx_isr_s cn63xxp1; 227 }; 228 229 union cvmx_mixx_orcnt { 230 uint64_t u64; 231 struct cvmx_mixx_orcnt_s { 232 uint64_t reserved_20_63:44; 233 uint64_t orcnt:20; 234 } s; 235 struct cvmx_mixx_orcnt_s cn52xx; 236 struct cvmx_mixx_orcnt_s cn52xxp1; 237 struct cvmx_mixx_orcnt_s cn56xx; 238 struct cvmx_mixx_orcnt_s cn56xxp1; 239 struct cvmx_mixx_orcnt_s cn63xx; 240 struct cvmx_mixx_orcnt_s cn63xxp1; 241 }; 242 243 union cvmx_mixx_orhwm { 244 uint64_t u64; 245 struct cvmx_mixx_orhwm_s { 246 uint64_t reserved_20_63:44; 247 uint64_t orhwm:20; 248 } s; 249 struct cvmx_mixx_orhwm_s cn52xx; 250 struct cvmx_mixx_orhwm_s cn52xxp1; 251 struct cvmx_mixx_orhwm_s cn56xx; 252 struct cvmx_mixx_orhwm_s cn56xxp1; 253 struct cvmx_mixx_orhwm_s cn63xx; 254 struct cvmx_mixx_orhwm_s cn63xxp1; 255 }; 256 257 union cvmx_mixx_oring1 { 258 uint64_t u64; 259 struct cvmx_mixx_oring1_s { 260 uint64_t reserved_60_63:4; 261 uint64_t osize:20; 262 uint64_t obase:37; 263 uint64_t reserved_0_2:3; 264 } s; 265 struct cvmx_mixx_oring1_cn52xx { 266 uint64_t reserved_60_63:4; 267 uint64_t osize:20; 268 uint64_t reserved_36_39:4; 269 uint64_t obase:33; 270 uint64_t reserved_0_2:3; 271 } cn52xx; 272 struct cvmx_mixx_oring1_cn52xx cn52xxp1; 273 struct cvmx_mixx_oring1_cn52xx cn56xx; 274 struct cvmx_mixx_oring1_cn52xx cn56xxp1; 275 struct cvmx_mixx_oring1_s cn63xx; 276 struct cvmx_mixx_oring1_s cn63xxp1; 277 }; 278 279 union cvmx_mixx_oring2 { 280 uint64_t u64; 281 struct cvmx_mixx_oring2_s { 282 uint64_t reserved_52_63:12; 283 uint64_t otlptr:20; 284 uint64_t reserved_20_31:12; 285 uint64_t odbell:20; 286 } s; 287 struct cvmx_mixx_oring2_s cn52xx; 288 struct cvmx_mixx_oring2_s cn52xxp1; 289 struct cvmx_mixx_oring2_s cn56xx; 290 struct cvmx_mixx_oring2_s cn56xxp1; 291 struct cvmx_mixx_oring2_s cn63xx; 292 struct cvmx_mixx_oring2_s cn63xxp1; 293 }; 294 295 union cvmx_mixx_remcnt { 296 uint64_t u64; 297 struct cvmx_mixx_remcnt_s { 298 uint64_t reserved_52_63:12; 299 uint64_t iremcnt:20; 300 uint64_t reserved_20_31:12; 301 uint64_t oremcnt:20; 302 } s; 303 struct cvmx_mixx_remcnt_s cn52xx; 304 struct cvmx_mixx_remcnt_s cn52xxp1; 305 struct cvmx_mixx_remcnt_s cn56xx; 306 struct cvmx_mixx_remcnt_s cn56xxp1; 307 struct cvmx_mixx_remcnt_s cn63xx; 308 struct cvmx_mixx_remcnt_s cn63xxp1; 309 }; 310 311 union cvmx_mixx_tsctl { 312 uint64_t u64; 313 struct cvmx_mixx_tsctl_s { 314 uint64_t reserved_21_63:43; 315 uint64_t tsavl:5; 316 uint64_t reserved_13_15:3; 317 uint64_t tstot:5; 318 uint64_t reserved_5_7:3; 319 uint64_t tscnt:5; 320 } s; 321 struct cvmx_mixx_tsctl_s cn63xx; 322 struct cvmx_mixx_tsctl_s cn63xxp1; 323 }; 324 325 union cvmx_mixx_tstamp { 326 uint64_t u64; 327 struct cvmx_mixx_tstamp_s { 328 uint64_t tstamp:64; 329 } s; 330 struct cvmx_mixx_tstamp_s cn63xx; 331 struct cvmx_mixx_tstamp_s cn63xxp1; 332 }; 333 334 #endif 335