1/*
2 * Miscellaneous low-level MMU functions.
3 *
4 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2008-2009 PetaLogix
6 * Copyright (C) 2007 Xilinx, Inc.  All rights reserved.
7 *
8 * Derived from arch/ppc/kernel/misc.S
9 *
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file COPYING in the main directory of this
12 * archive for more details.
13 */
14
15#include <linux/linkage.h>
16#include <linux/sys.h>
17#include <asm/unistd.h>
18#include <linux/errno.h>
19#include <asm/mmu.h>
20#include <asm/page.h>
21
22	.text
23/*
24 * Flush MMU TLB
25 *
26 * We avoid flushing the pinned 0, 1 and possibly 2 entries.
27 */
28.globl _tlbia;
29.type  _tlbia, @function
30.align 4;
31_tlbia:
32	addik	r12, r0, MICROBLAZE_TLB_SIZE - 1 /* flush all entries (63 - 3) */
33	/* isync */
34_tlbia_1:
35	mts	rtlbx, r12
36	nop
37	mts	rtlbhi, r0 /* flush: ensure V is clear */
38	nop
39	addik	r11, r12, -2
40	bneid	r11, _tlbia_1 /* loop for all entries */
41	addik	r12, r12, -1
42	/* sync */
43	rtsd	r15, 8
44	nop
45	.size  _tlbia, . - _tlbia
46
47/*
48 * Flush MMU TLB for a particular address (in r5)
49 */
50.globl _tlbie;
51.type  _tlbie, @function
52.align 4;
53_tlbie:
54	mts	rtlbsx, r5 /* look up the address in TLB */
55	nop
56	mfs	r12, rtlbx /* Retrieve index */
57	nop
58	blti	r12, _tlbie_1 /* Check if found */
59	mts	rtlbhi, r0 /* flush: ensure V is clear */
60	nop
61_tlbie_1:
62	rtsd	r15, 8
63	nop
64
65	.size  _tlbie, . - _tlbie
66
67/*
68 * Allocate TLB entry for early console
69 */
70.globl early_console_reg_tlb_alloc;
71.type  early_console_reg_tlb_alloc, @function
72.align 4;
73early_console_reg_tlb_alloc:
74	/*
75	 * Load a TLB entry for the UART, so that microblaze_progress() can use
76	 * the UARTs nice and early.  We use a 4k real==virtual mapping.
77	 */
78	ori	r4, r0, MICROBLAZE_TLB_SIZE - 1
79	mts	rtlbx, r4 /* TLB slot 63 */
80
81	or	r4,r5,r0
82	andi	r4,r4,0xfffff000
83	ori	r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
84
85	andi	r5,r5,0xfffff000
86	ori	r5,r5,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
87
88	mts	rtlblo,r4 /* Load the data portion of the entry */
89	nop
90	mts	rtlbhi,r5 /* Load the tag portion of the entry */
91	nop
92	rtsd	r15, 8
93	nop
94
95	.size  early_console_reg_tlb_alloc, . - early_console_reg_tlb_alloc
96