1 /*
2 * linux/arch/m32r/platforms/m32700ut/setup.c
3 *
4 * Setup routines for Renesas M32700UT Board
5 *
6 * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto, Takeo Takahashi
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
12 */
13
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18
19 #include <asm/system.h>
20 #include <asm/m32r.h>
21 #include <asm/io.h>
22
23 /*
24 * M32700 Interrupt Control Unit (Level 1)
25 */
26 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
27
28 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
29
disable_m32700ut_irq(unsigned int irq)30 static void disable_m32700ut_irq(unsigned int irq)
31 {
32 unsigned long port, data;
33
34 port = irq2port(irq);
35 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
36 outl(data, port);
37 }
38
enable_m32700ut_irq(unsigned int irq)39 static void enable_m32700ut_irq(unsigned int irq)
40 {
41 unsigned long port, data;
42
43 port = irq2port(irq);
44 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
45 outl(data, port);
46 }
47
mask_m32700ut(struct irq_data * data)48 static void mask_m32700ut(struct irq_data *data)
49 {
50 disable_m32700ut_irq(data->irq);
51 }
52
unmask_m32700ut(struct irq_data * data)53 static void unmask_m32700ut(struct irq_data *data)
54 {
55 enable_m32700ut_irq(data->irq);
56 }
57
shutdown_m32700ut(struct irq_data * data)58 static void shutdown_m32700ut(struct irq_data *data)
59 {
60 unsigned long port;
61
62 port = irq2port(data->irq);
63 outl(M32R_ICUCR_ILEVEL7, port);
64 }
65
66 static struct irq_chip m32700ut_irq_type =
67 {
68 .name = "M32700UT-IRQ",
69 .irq_shutdown = shutdown_m32700ut,
70 .irq_mask = mask_m32700ut,
71 .irq_unmask = unmask_m32700ut
72 };
73
74 /*
75 * Interrupt Control Unit of PLD on M32700UT (Level 2)
76 */
77 #define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
78 #define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
79 (((x) - 1) * sizeof(unsigned short)))
80
81 typedef struct {
82 unsigned short icucr; /* ICU Control Register */
83 } pld_icu_data_t;
84
85 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
86
disable_m32700ut_pld_irq(unsigned int irq)87 static void disable_m32700ut_pld_irq(unsigned int irq)
88 {
89 unsigned long port, data;
90 unsigned int pldirq;
91
92 pldirq = irq2pldirq(irq);
93 port = pldirq2port(pldirq);
94 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
95 outw(data, port);
96 }
97
enable_m32700ut_pld_irq(unsigned int irq)98 static void enable_m32700ut_pld_irq(unsigned int irq)
99 {
100 unsigned long port, data;
101 unsigned int pldirq;
102
103 pldirq = irq2pldirq(irq);
104 port = pldirq2port(pldirq);
105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
106 outw(data, port);
107 }
108
mask_m32700ut_pld(struct irq_data * data)109 static void mask_m32700ut_pld(struct irq_data *data)
110 {
111 disable_m32700ut_pld_irq(data->irq);
112 }
113
unmask_m32700ut_pld(struct irq_data * data)114 static void unmask_m32700ut_pld(struct irq_data *data)
115 {
116 enable_m32700ut_pld_irq(data->irq);
117 enable_m32700ut_irq(M32R_IRQ_INT1);
118 }
119
shutdown_m32700ut_pld_irq(struct irq_data * data)120 static void shutdown_m32700ut_pld_irq(struct irq_data *data)
121 {
122 unsigned long port;
123 unsigned int pldirq;
124
125 pldirq = irq2pldirq(data->irq);
126 port = pldirq2port(pldirq);
127 outw(PLD_ICUCR_ILEVEL7, port);
128 }
129
130 static struct irq_chip m32700ut_pld_irq_type =
131 {
132 .name = "M32700UT-PLD-IRQ",
133 .irq_shutdown = shutdown_m32700ut_pld_irq,
134 .irq_mask = mask_m32700ut_pld,
135 .irq_unmask = unmask_m32700ut_pld,
136 };
137
138 /*
139 * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
140 */
141 #define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
142 #define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
143 (((x) - 1) * sizeof(unsigned short)))
144
145 static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
146
disable_m32700ut_lanpld_irq(unsigned int irq)147 static void disable_m32700ut_lanpld_irq(unsigned int irq)
148 {
149 unsigned long port, data;
150 unsigned int pldirq;
151
152 pldirq = irq2lanpldirq(irq);
153 port = lanpldirq2port(pldirq);
154 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
155 outw(data, port);
156 }
157
enable_m32700ut_lanpld_irq(unsigned int irq)158 static void enable_m32700ut_lanpld_irq(unsigned int irq)
159 {
160 unsigned long port, data;
161 unsigned int pldirq;
162
163 pldirq = irq2lanpldirq(irq);
164 port = lanpldirq2port(pldirq);
165 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
166 outw(data, port);
167 }
168
mask_m32700ut_lanpld(struct irq_data * data)169 static void mask_m32700ut_lanpld(struct irq_data *data)
170 {
171 disable_m32700ut_lanpld_irq(data->irq);
172 }
173
unmask_m32700ut_lanpld(struct irq_data * data)174 static void unmask_m32700ut_lanpld(struct irq_data *data)
175 {
176 enable_m32700ut_lanpld_irq(data->irq);
177 enable_m32700ut_irq(M32R_IRQ_INT0);
178 }
179
shutdown_m32700ut_lanpld(struct irq_data * data)180 static void shutdown_m32700ut_lanpld(struct irq_data *data)
181 {
182 unsigned long port;
183 unsigned int pldirq;
184
185 pldirq = irq2lanpldirq(data->irq);
186 port = lanpldirq2port(pldirq);
187 outw(PLD_ICUCR_ILEVEL7, port);
188 }
189
190 static struct irq_chip m32700ut_lanpld_irq_type =
191 {
192 .name = "M32700UT-PLD-LAN-IRQ",
193 .irq_shutdown = shutdown_m32700ut_lanpld,
194 .irq_mask = mask_m32700ut_lanpld,
195 .irq_unmask = unmask_m32700ut_lanpld,
196 };
197
198 /*
199 * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
200 */
201 #define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
202 #define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
203 (((x) - 1) * sizeof(unsigned short)))
204
205 static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
206
disable_m32700ut_lcdpld_irq(unsigned int irq)207 static void disable_m32700ut_lcdpld_irq(unsigned int irq)
208 {
209 unsigned long port, data;
210 unsigned int pldirq;
211
212 pldirq = irq2lcdpldirq(irq);
213 port = lcdpldirq2port(pldirq);
214 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
215 outw(data, port);
216 }
217
enable_m32700ut_lcdpld_irq(unsigned int irq)218 static void enable_m32700ut_lcdpld_irq(unsigned int irq)
219 {
220 unsigned long port, data;
221 unsigned int pldirq;
222
223 pldirq = irq2lcdpldirq(irq);
224 port = lcdpldirq2port(pldirq);
225 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
226 outw(data, port);
227 }
228
mask_m32700ut_lcdpld(struct irq_data * data)229 static void mask_m32700ut_lcdpld(struct irq_data *data)
230 {
231 disable_m32700ut_lcdpld_irq(data->irq);
232 }
233
unmask_m32700ut_lcdpld(struct irq_data * data)234 static void unmask_m32700ut_lcdpld(struct irq_data *data)
235 {
236 enable_m32700ut_lcdpld_irq(data->irq);
237 enable_m32700ut_irq(M32R_IRQ_INT2);
238 }
239
shutdown_m32700ut_lcdpld(struct irq_data * data)240 static void shutdown_m32700ut_lcdpld(struct irq_data *data)
241 {
242 unsigned long port;
243 unsigned int pldirq;
244
245 pldirq = irq2lcdpldirq(data->irq);
246 port = lcdpldirq2port(pldirq);
247 outw(PLD_ICUCR_ILEVEL7, port);
248 }
249
250 static struct irq_chip m32700ut_lcdpld_irq_type =
251 {
252 .name = "M32700UT-PLD-LCD-IRQ",
253 .irq_shutdown = shutdown_m32700ut_lcdpld,
254 .irq_mask = mask_m32700ut_lcdpld,
255 .irq_unmask = unmask_m32700ut_lcdpld,
256 };
257
init_IRQ(void)258 void __init init_IRQ(void)
259 {
260 #if defined(CONFIG_SMC91X)
261 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
262 irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN,
263 &m32700ut_lanpld_irq_type, handle_level_irq);
264 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
265 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
266 #endif /* CONFIG_SMC91X */
267
268 /* MFT2 : system timer */
269 irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
270 handle_level_irq);
271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
272 disable_m32700ut_irq(M32R_IRQ_MFT2);
273
274 /* SIO0 : receive */
275 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
276 handle_level_irq);
277 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
278 disable_m32700ut_irq(M32R_IRQ_SIO0_R);
279
280 /* SIO0 : send */
281 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
282 handle_level_irq);
283 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
284 disable_m32700ut_irq(M32R_IRQ_SIO0_S);
285
286 /* SIO1 : receive */
287 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
288 handle_level_irq);
289 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
290 disable_m32700ut_irq(M32R_IRQ_SIO1_R);
291
292 /* SIO1 : send */
293 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
294 handle_level_irq);
295 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
296 disable_m32700ut_irq(M32R_IRQ_SIO1_S);
297
298 /* DMA1 : */
299 irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
300 handle_level_irq);
301 icu_data[M32R_IRQ_DMA1].icucr = 0;
302 disable_m32700ut_irq(M32R_IRQ_DMA1);
303
304 #ifdef CONFIG_SERIAL_M32R_PLDSIO
305 /* INT#1: SIO0 Receive on PLD */
306 irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
307 handle_level_irq);
308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
309 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
310
311 /* INT#1: SIO0 Send on PLD */
312 irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
313 handle_level_irq);
314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
315 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
316 #endif /* CONFIG_SERIAL_M32R_PLDSIO */
317
318 /* INT#1: CFC IREQ on PLD */
319 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
320 handle_level_irq);
321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
322 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
323
324 /* INT#1: CFC Insert on PLD */
325 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
326 handle_level_irq);
327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
328 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
329
330 /* INT#1: CFC Eject on PLD */
331 irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
332 handle_level_irq);
333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
334 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
335
336 /*
337 * INT0# is used for LAN, DIO
338 * We enable it here.
339 */
340 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
341 enable_m32700ut_irq(M32R_IRQ_INT0);
342
343 /*
344 * INT1# is used for UART, MMC, CF Controller in FPGA.
345 * We enable it here.
346 */
347 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
348 enable_m32700ut_irq(M32R_IRQ_INT1);
349
350 #if defined(CONFIG_USB)
351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
352 irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
353 &m32700ut_lcdpld_irq_type, handle_level_irq);
354
355 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
356 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
357 #endif
358 /*
359 * INT2# is used for BAT, USB, AUDIO
360 * We enable it here.
361 */
362 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
363 enable_m32700ut_irq(M32R_IRQ_INT2);
364
365 #if defined(CONFIG_VIDEO_M32R_AR)
366 /*
367 * INT3# is used for AR
368 */
369 irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
370 handle_level_irq);
371 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
372 disable_m32700ut_irq(M32R_IRQ_INT3);
373 #endif /* CONFIG_VIDEO_M32R_AR */
374 }
375
376 #if defined(CONFIG_SMC91X)
377
378 #define LAN_IOSTART 0x300
379 #define LAN_IOEND 0x320
380 static struct resource smc91x_resources[] = {
381 [0] = {
382 .start = (LAN_IOSTART),
383 .end = (LAN_IOEND),
384 .flags = IORESOURCE_MEM,
385 },
386 [1] = {
387 .start = M32700UT_LAN_IRQ_LAN,
388 .end = M32700UT_LAN_IRQ_LAN,
389 .flags = IORESOURCE_IRQ,
390 }
391 };
392
393 static struct platform_device smc91x_device = {
394 .name = "smc91x",
395 .id = 0,
396 .num_resources = ARRAY_SIZE(smc91x_resources),
397 .resource = smc91x_resources,
398 };
399 #endif
400
401 #if defined(CONFIG_FB_S1D13XXX)
402
403 #include <video/s1d13xxxfb.h>
404 #include <asm/s1d13806.h>
405
406 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
407 .initregs = s1d13xxxfb_initregs,
408 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
409 .platform_init_video = NULL,
410 #ifdef CONFIG_PM
411 .platform_suspend_video = NULL,
412 .platform_resume_video = NULL,
413 #endif
414 };
415
416 static struct resource s1d13xxxfb_resources[] = {
417 [0] = {
418 .start = 0x10600000UL,
419 .end = 0x1073FFFFUL,
420 .flags = IORESOURCE_MEM,
421 },
422 [1] = {
423 .start = 0x10400000UL,
424 .end = 0x104001FFUL,
425 .flags = IORESOURCE_MEM,
426 }
427 };
428
429 static struct platform_device s1d13xxxfb_device = {
430 .name = S1D_DEVICENAME,
431 .id = 0,
432 .dev = {
433 .platform_data = &s1d13xxxfb_data,
434 },
435 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
436 .resource = s1d13xxxfb_resources,
437 };
438 #endif
439
platform_init(void)440 static int __init platform_init(void)
441 {
442 #if defined(CONFIG_SMC91X)
443 platform_device_register(&smc91x_device);
444 #endif
445 #if defined(CONFIG_FB_S1D13XXX)
446 platform_device_register(&s1d13xxxfb_device);
447 #endif
448 return 0;
449 }
450 arch_initcall(platform_init);
451