1 /* linux/arch/arm/plat-s3c24xx/pm.c
2  *
3  * Copyright (c) 2004-2006 Simtec Electronics
4  *	Ben Dooks <ben@simtec.co.uk>
5  *
6  * S3C24XX Power Manager (Suspend-To-RAM) support
7  *
8  * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
23  *
24  * Parts based on arch/arm/mach-pxa/pm.c
25  *
26  * Thanks to Dimitry Andric for debugging
27 */
28 
29 #include <linux/init.h>
30 #include <linux/suspend.h>
31 #include <linux/errno.h>
32 #include <linux/time.h>
33 #include <linux/gpio.h>
34 #include <linux/interrupt.h>
35 #include <linux/serial_core.h>
36 #include <linux/io.h>
37 
38 #include <plat/regs-serial.h>
39 #include <mach/regs-clock.h>
40 #include <mach/regs-gpio.h>
41 #include <mach/regs-mem.h>
42 #include <mach/regs-irq.h>
43 
44 #include <asm/mach/time.h>
45 
46 #include <plat/gpio-cfg.h>
47 #include <plat/pm.h>
48 
49 #define PFX "s3c24xx-pm: "
50 
51 static struct sleep_save core_save[] = {
52 	SAVE_ITEM(S3C2410_LOCKTIME),
53 	SAVE_ITEM(S3C2410_CLKCON),
54 
55 	/* we restore the timings here, with the proviso that the board
56 	 * brings the system up in an slower, or equal frequency setting
57 	 * to the original system.
58 	 *
59 	 * if we cannot guarantee this, then things are going to go very
60 	 * wrong here, as we modify the refresh and both pll settings.
61 	 */
62 
63 	SAVE_ITEM(S3C2410_BWSCON),
64 	SAVE_ITEM(S3C2410_BANKCON0),
65 	SAVE_ITEM(S3C2410_BANKCON1),
66 	SAVE_ITEM(S3C2410_BANKCON2),
67 	SAVE_ITEM(S3C2410_BANKCON3),
68 	SAVE_ITEM(S3C2410_BANKCON4),
69 	SAVE_ITEM(S3C2410_BANKCON5),
70 
71 #ifndef CONFIG_CPU_FREQ
72 	SAVE_ITEM(S3C2410_CLKDIVN),
73 	SAVE_ITEM(S3C2410_MPLLCON),
74 	SAVE_ITEM(S3C2410_REFRESH),
75 #endif
76 	SAVE_ITEM(S3C2410_UPLLCON),
77 	SAVE_ITEM(S3C2410_CLKSLOW),
78 };
79 
80 static struct sleep_save misc_save[] = {
81 	SAVE_ITEM(S3C2410_DCLKCON),
82 };
83 
84 /* s3c_pm_check_resume_pin
85  *
86  * check to see if the pin is configured correctly for sleep mode, and
87  * make any necessary adjustments if it is not
88 */
89 
s3c_pm_check_resume_pin(unsigned int pin,unsigned int irqoffs)90 static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
91 {
92 	unsigned long irqstate;
93 	unsigned long pinstate;
94 	int irq = gpio_to_irq(pin);
95 
96 	if (irqoffs < 4)
97 		irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
98 	else
99 		irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
100 
101 	pinstate = s3c_gpio_getcfg(pin);
102 
103 	if (!irqstate) {
104 		if (pinstate == S3C2410_GPIO_IRQ)
105 			S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
106 	} else {
107 		if (pinstate == S3C2410_GPIO_IRQ) {
108 			S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
109 			s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
110 		}
111 	}
112 }
113 
114 /* s3c_pm_configure_extint
115  *
116  * configure all external interrupt pins
117 */
118 
s3c_pm_configure_extint(void)119 void s3c_pm_configure_extint(void)
120 {
121 	int pin;
122 
123 	/* for each of the external interrupts (EINT0..EINT15) we
124 	 * need to check wether it is an external interrupt source,
125 	 * and then configure it as an input if it is not
126 	*/
127 
128 	for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
129 		s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
130 	}
131 
132 	for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
133 		s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
134 	}
135 }
136 
137 
s3c_pm_restore_core(void)138 void s3c_pm_restore_core(void)
139 {
140 	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
141 	s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
142 }
143 
s3c_pm_save_core(void)144 void s3c_pm_save_core(void)
145 {
146 	s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
147 	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
148 }
149 
150