1 /* linux/include/asm-arm/plat-s3c24xx/irq.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU IRQ support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/io.h>
14
15 #include <mach/hardware.h>
16 #include <mach/regs-irq.h>
17 #include <mach/regs-gpio.h>
18
19 #define irqdbf(x...)
20 #define irqdbf2(x...)
21
22 #define EXTINT_OFF (IRQ_EINT4 - 4)
23
24 /* these are exported for arch/arm/mach-* usage */
25 extern struct irq_chip s3c_irq_level_chip;
26 extern struct irq_chip s3c_irq_chip;
27
28 static inline void
s3c_irqsub_mask(unsigned int irqno,unsigned int parentbit,int subcheck)29 s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
30 int subcheck)
31 {
32 unsigned long mask;
33 unsigned long submask;
34
35 submask = __raw_readl(S3C2410_INTSUBMSK);
36 mask = __raw_readl(S3C2410_INTMSK);
37
38 submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
39
40 /* check to see if we need to mask the parent IRQ */
41
42 if ((submask & subcheck) == subcheck) {
43 __raw_writel(mask | parentbit, S3C2410_INTMSK);
44 }
45
46 /* write back masks */
47 __raw_writel(submask, S3C2410_INTSUBMSK);
48
49 }
50
51 static inline void
s3c_irqsub_unmask(unsigned int irqno,unsigned int parentbit)52 s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
53 {
54 unsigned long mask;
55 unsigned long submask;
56
57 submask = __raw_readl(S3C2410_INTSUBMSK);
58 mask = __raw_readl(S3C2410_INTMSK);
59
60 submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
61 mask &= ~parentbit;
62
63 /* write back masks */
64 __raw_writel(submask, S3C2410_INTSUBMSK);
65 __raw_writel(mask, S3C2410_INTMSK);
66 }
67
68
69 static inline void
s3c_irqsub_maskack(unsigned int irqno,unsigned int parentmask,unsigned int group)70 s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
71 {
72 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
73
74 s3c_irqsub_mask(irqno, parentmask, group);
75
76 __raw_writel(bit, S3C2410_SUBSRCPND);
77
78 /* only ack parent if we've got all the irqs (seems we must
79 * ack, all and hope that the irq system retriggers ok when
80 * the interrupt goes off again)
81 */
82
83 if (1) {
84 __raw_writel(parentmask, S3C2410_SRCPND);
85 __raw_writel(parentmask, S3C2410_INTPND);
86 }
87 }
88
89 static inline void
s3c_irqsub_ack(unsigned int irqno,unsigned int parentmask,unsigned int group)90 s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
91 {
92 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
93
94 __raw_writel(bit, S3C2410_SUBSRCPND);
95
96 /* only ack parent if we've got all the irqs (seems we must
97 * ack, all and hope that the irq system retriggers ok when
98 * the interrupt goes off again)
99 */
100
101 if (1) {
102 __raw_writel(parentmask, S3C2410_SRCPND);
103 __raw_writel(parentmask, S3C2410_INTPND);
104 }
105 }
106
107 /* exported for use in arch/arm/mach-s3c2410 */
108
109 #ifdef CONFIG_PM
110 extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
111 #else
112 #define s3c_irq_wake NULL
113 #endif
114
115 extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
116