1 /*
2 * linux/arch/arm/plat-mxc/time.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/clockchips.h>
27 #include <linux/clk.h>
28
29 #include <mach/hardware.h>
30 #include <asm/sched_clock.h>
31 #include <asm/mach/time.h>
32 #include <mach/common.h>
33
34 /*
35 * There are 2 versions of the timer hardware on Freescale MXC hardware.
36 * Version 1: MX1/MXL, MX21, MX27.
37 * Version 2: MX25, MX31, MX35, MX37, MX51
38 */
39
40 /* defines common for all i.MX */
41 #define MXC_TCTL 0x00
42 #define MXC_TCTL_TEN (1 << 0) /* Enable module */
43 #define MXC_TPRER 0x04
44
45 /* MX1, MX21, MX27 */
46 #define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
47 #define MX1_2_TCTL_IRQEN (1 << 4)
48 #define MX1_2_TCTL_FRR (1 << 8)
49 #define MX1_2_TCMP 0x08
50 #define MX1_2_TCN 0x10
51 #define MX1_2_TSTAT 0x14
52
53 /* MX21, MX27 */
54 #define MX2_TSTAT_CAPT (1 << 1)
55 #define MX2_TSTAT_COMP (1 << 0)
56
57 /* MX31, MX35, MX25, MXC91231, MX5 */
58 #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
59 #define V2_TCTL_CLK_IPG (1 << 6)
60 #define V2_TCTL_FRR (1 << 9)
61 #define V2_IR 0x0c
62 #define V2_TSTAT 0x08
63 #define V2_TSTAT_OF1 (1 << 0)
64 #define V2_TCN 0x24
65 #define V2_TCMP 0x10
66
67 #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
68 #define timer_is_v2() (!timer_is_v1())
69
70 static struct clock_event_device clockevent_mxc;
71 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
72
73 static void __iomem *timer_base;
74
gpt_irq_disable(void)75 static inline void gpt_irq_disable(void)
76 {
77 unsigned int tmp;
78
79 if (timer_is_v2())
80 __raw_writel(0, timer_base + V2_IR);
81 else {
82 tmp = __raw_readl(timer_base + MXC_TCTL);
83 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
84 }
85 }
86
gpt_irq_enable(void)87 static inline void gpt_irq_enable(void)
88 {
89 if (timer_is_v2())
90 __raw_writel(1<<0, timer_base + V2_IR);
91 else {
92 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
93 timer_base + MXC_TCTL);
94 }
95 }
96
gpt_irq_acknowledge(void)97 static void gpt_irq_acknowledge(void)
98 {
99 if (timer_is_v1()) {
100 if (cpu_is_mx1())
101 __raw_writel(0, timer_base + MX1_2_TSTAT);
102 else
103 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
104 timer_base + MX1_2_TSTAT);
105 } else if (timer_is_v2())
106 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
107 }
108
dummy_get_cycles(struct clocksource * cs)109 static cycle_t dummy_get_cycles(struct clocksource *cs)
110 {
111 return 0;
112 }
113
mx1_2_get_cycles(struct clocksource * cs)114 static cycle_t mx1_2_get_cycles(struct clocksource *cs)
115 {
116 return __raw_readl(timer_base + MX1_2_TCN);
117 }
118
v2_get_cycles(struct clocksource * cs)119 static cycle_t v2_get_cycles(struct clocksource *cs)
120 {
121 return __raw_readl(timer_base + V2_TCN);
122 }
123
124 static struct clocksource clocksource_mxc = {
125 .name = "mxc_timer1",
126 .rating = 200,
127 .read = dummy_get_cycles,
128 .mask = CLOCKSOURCE_MASK(32),
129 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
130 };
131
132 static DEFINE_CLOCK_DATA(cd);
sched_clock(void)133 unsigned long long notrace sched_clock(void)
134 {
135 cycle_t cyc = clocksource_mxc.read(&clocksource_mxc);
136
137 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
138 }
139
mxc_update_sched_clock(void)140 static void notrace mxc_update_sched_clock(void)
141 {
142 cycle_t cyc = clocksource_mxc.read(&clocksource_mxc);
143 update_sched_clock(&cd, cyc, (u32)~0);
144 }
145
mxc_clocksource_init(struct clk * timer_clk)146 static int __init mxc_clocksource_init(struct clk *timer_clk)
147 {
148 unsigned int c = clk_get_rate(timer_clk);
149
150 if (timer_is_v2())
151 clocksource_mxc.read = v2_get_cycles;
152 else
153 clocksource_mxc.read = mx1_2_get_cycles;
154
155 init_sched_clock(&cd, mxc_update_sched_clock, 32, c);
156 clocksource_register_hz(&clocksource_mxc, c);
157
158 return 0;
159 }
160
161 /* clock event */
162
mx1_2_set_next_event(unsigned long evt,struct clock_event_device * unused)163 static int mx1_2_set_next_event(unsigned long evt,
164 struct clock_event_device *unused)
165 {
166 unsigned long tcmp;
167
168 tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
169
170 __raw_writel(tcmp, timer_base + MX1_2_TCMP);
171
172 return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
173 -ETIME : 0;
174 }
175
v2_set_next_event(unsigned long evt,struct clock_event_device * unused)176 static int v2_set_next_event(unsigned long evt,
177 struct clock_event_device *unused)
178 {
179 unsigned long tcmp;
180
181 tcmp = __raw_readl(timer_base + V2_TCN) + evt;
182
183 __raw_writel(tcmp, timer_base + V2_TCMP);
184
185 return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
186 -ETIME : 0;
187 }
188
189 #ifdef DEBUG
190 static const char *clock_event_mode_label[] = {
191 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
192 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
193 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
194 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
195 };
196 #endif /* DEBUG */
197
mxc_set_mode(enum clock_event_mode mode,struct clock_event_device * evt)198 static void mxc_set_mode(enum clock_event_mode mode,
199 struct clock_event_device *evt)
200 {
201 unsigned long flags;
202
203 /*
204 * The timer interrupt generation is disabled at least
205 * for enough time to call mxc_set_next_event()
206 */
207 local_irq_save(flags);
208
209 /* Disable interrupt in GPT module */
210 gpt_irq_disable();
211
212 if (mode != clockevent_mode) {
213 /* Set event time into far-far future */
214 if (timer_is_v2())
215 __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
216 timer_base + V2_TCMP);
217 else
218 __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
219 timer_base + MX1_2_TCMP);
220
221 /* Clear pending interrupt */
222 gpt_irq_acknowledge();
223 }
224
225 #ifdef DEBUG
226 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
227 clock_event_mode_label[clockevent_mode],
228 clock_event_mode_label[mode]);
229 #endif /* DEBUG */
230
231 /* Remember timer mode */
232 clockevent_mode = mode;
233 local_irq_restore(flags);
234
235 switch (mode) {
236 case CLOCK_EVT_MODE_PERIODIC:
237 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
238 "supported for i.MX\n");
239 break;
240 case CLOCK_EVT_MODE_ONESHOT:
241 /*
242 * Do not put overhead of interrupt enable/disable into
243 * mxc_set_next_event(), the core has about 4 minutes
244 * to call mxc_set_next_event() or shutdown clock after
245 * mode switching
246 */
247 local_irq_save(flags);
248 gpt_irq_enable();
249 local_irq_restore(flags);
250 break;
251 case CLOCK_EVT_MODE_SHUTDOWN:
252 case CLOCK_EVT_MODE_UNUSED:
253 case CLOCK_EVT_MODE_RESUME:
254 /* Left event sources disabled, no more interrupts appear */
255 break;
256 }
257 }
258
259 /*
260 * IRQ handler for the timer
261 */
mxc_timer_interrupt(int irq,void * dev_id)262 static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
263 {
264 struct clock_event_device *evt = &clockevent_mxc;
265 uint32_t tstat;
266
267 if (timer_is_v2())
268 tstat = __raw_readl(timer_base + V2_TSTAT);
269 else
270 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
271
272 gpt_irq_acknowledge();
273
274 evt->event_handler(evt);
275
276 return IRQ_HANDLED;
277 }
278
279 static struct irqaction mxc_timer_irq = {
280 .name = "i.MX Timer Tick",
281 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
282 .handler = mxc_timer_interrupt,
283 };
284
285 static struct clock_event_device clockevent_mxc = {
286 .name = "mxc_timer1",
287 .features = CLOCK_EVT_FEAT_ONESHOT,
288 .shift = 32,
289 .set_mode = mxc_set_mode,
290 .set_next_event = mx1_2_set_next_event,
291 .rating = 200,
292 };
293
mxc_clockevent_init(struct clk * timer_clk)294 static int __init mxc_clockevent_init(struct clk *timer_clk)
295 {
296 unsigned int c = clk_get_rate(timer_clk);
297
298 if (timer_is_v2())
299 clockevent_mxc.set_next_event = v2_set_next_event;
300
301 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
302 clockevent_mxc.shift);
303 clockevent_mxc.max_delta_ns =
304 clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
305 clockevent_mxc.min_delta_ns =
306 clockevent_delta2ns(0xff, &clockevent_mxc);
307
308 clockevent_mxc.cpumask = cpumask_of(0);
309
310 clockevents_register_device(&clockevent_mxc);
311
312 return 0;
313 }
314
mxc_timer_init(struct clk * timer_clk,void __iomem * base,int irq)315 void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
316 {
317 uint32_t tctl_val;
318
319 clk_enable(timer_clk);
320
321 timer_base = base;
322
323 /*
324 * Initialise to a known state (all timers off, and timing reset)
325 */
326
327 __raw_writel(0, timer_base + MXC_TCTL);
328 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
329
330 if (timer_is_v2())
331 tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
332 else
333 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
334
335 __raw_writel(tctl_val, timer_base + MXC_TCTL);
336
337 /* init and register the timer to the framework */
338 mxc_clocksource_init(timer_clk);
339 mxc_clockevent_init(timer_clk);
340
341 /* Make irqs happen */
342 setup_irq(irq, &mxc_timer_irq);
343 }
344