1 /*
2  * Copyright (C) 2010,2011 Google, Inc.
3  *
4  * Author:
5  *	Colin Cross <ccross@android.com>
6  *	Erik Gilling <ccross@android.com>
7  *
8  * This software is licensed under the terms of the GNU General Public
9  * License version 2, as published by the Free Software Foundation, and
10  * may be copied, distributed, and modified under those terms.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18 
19 
20 #include <linux/resource.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/fsl_devices.h>
24 #include <linux/serial_8250.h>
25 #include <asm/pmu.h>
26 #include <mach/irqs.h>
27 #include <mach/iomap.h>
28 #include <mach/dma.h>
29 
30 static struct resource i2c_resource1[] = {
31 	[0] = {
32 		.start	= INT_I2C,
33 		.end	= INT_I2C,
34 		.flags	= IORESOURCE_IRQ,
35 	},
36 	[1] = {
37 		.start	= TEGRA_I2C_BASE,
38 		.end	= TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
39 		.flags	= IORESOURCE_MEM,
40 	},
41 };
42 
43 static struct resource i2c_resource2[] = {
44 	[0] = {
45 		.start	= INT_I2C2,
46 		.end	= INT_I2C2,
47 		.flags	= IORESOURCE_IRQ,
48 	},
49 	[1] = {
50 		.start	= TEGRA_I2C2_BASE,
51 		.end	= TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
52 		.flags	= IORESOURCE_MEM,
53 	},
54 };
55 
56 static struct resource i2c_resource3[] = {
57 	[0] = {
58 		.start	= INT_I2C3,
59 		.end	= INT_I2C3,
60 		.flags	= IORESOURCE_IRQ,
61 	},
62 	[1] = {
63 		.start	= TEGRA_I2C3_BASE,
64 		.end	= TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
65 		.flags	= IORESOURCE_MEM,
66 	},
67 };
68 
69 static struct resource i2c_resource4[] = {
70 	[0] = {
71 		.start	= INT_DVC,
72 		.end	= INT_DVC,
73 		.flags	= IORESOURCE_IRQ,
74 	},
75 	[1] = {
76 		.start	= TEGRA_DVC_BASE,
77 		.end	= TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
78 		.flags	= IORESOURCE_MEM,
79 	},
80 };
81 
82 struct platform_device tegra_i2c_device1 = {
83 	.name		= "tegra-i2c",
84 	.id		= 0,
85 	.resource	= i2c_resource1,
86 	.num_resources	= ARRAY_SIZE(i2c_resource1),
87 	.dev = {
88 		.platform_data = 0,
89 	},
90 };
91 
92 struct platform_device tegra_i2c_device2 = {
93 	.name		= "tegra-i2c",
94 	.id		= 1,
95 	.resource	= i2c_resource2,
96 	.num_resources	= ARRAY_SIZE(i2c_resource2),
97 	.dev = {
98 		.platform_data = 0,
99 	},
100 };
101 
102 struct platform_device tegra_i2c_device3 = {
103 	.name		= "tegra-i2c",
104 	.id		= 2,
105 	.resource	= i2c_resource3,
106 	.num_resources	= ARRAY_SIZE(i2c_resource3),
107 	.dev = {
108 		.platform_data = 0,
109 	},
110 };
111 
112 struct platform_device tegra_i2c_device4 = {
113 	.name		= "tegra-i2c",
114 	.id		= 3,
115 	.resource	= i2c_resource4,
116 	.num_resources	= ARRAY_SIZE(i2c_resource4),
117 	.dev = {
118 		.platform_data = 0,
119 	},
120 };
121 
122 static struct resource spi_resource1[] = {
123 	[0] = {
124 		.start	= INT_S_LINK1,
125 		.end	= INT_S_LINK1,
126 		.flags	= IORESOURCE_IRQ,
127 	},
128 	[1] = {
129 		.start	= TEGRA_SPI1_BASE,
130 		.end	= TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
131 		.flags	= IORESOURCE_MEM,
132 	},
133 };
134 
135 static struct resource spi_resource2[] = {
136 	[0] = {
137 		.start	= INT_SPI_2,
138 		.end	= INT_SPI_2,
139 		.flags	= IORESOURCE_IRQ,
140 	},
141 	[1] = {
142 		.start	= TEGRA_SPI2_BASE,
143 		.end	= TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
144 		.flags	= IORESOURCE_MEM,
145 	},
146 };
147 
148 static struct resource spi_resource3[] = {
149 	[0] = {
150 		.start	= INT_SPI_3,
151 		.end	= INT_SPI_3,
152 		.flags	= IORESOURCE_IRQ,
153 	},
154 	[1] = {
155 		.start	= TEGRA_SPI3_BASE,
156 		.end	= TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
157 		.flags	= IORESOURCE_MEM,
158 	},
159 };
160 
161 static struct resource spi_resource4[] = {
162 	[0] = {
163 		.start	= INT_SPI_4,
164 		.end	= INT_SPI_4,
165 		.flags	= IORESOURCE_IRQ,
166 	},
167 	[1] = {
168 		.start	= TEGRA_SPI4_BASE,
169 		.end	= TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
170 		.flags	= IORESOURCE_MEM,
171 	},
172 };
173 
174 struct platform_device tegra_spi_device1 = {
175 	.name		= "spi_tegra",
176 	.id		= 0,
177 	.resource	= spi_resource1,
178 	.num_resources	= ARRAY_SIZE(spi_resource1),
179 	.dev		= {
180 		.coherent_dma_mask	= 0xffffffff,
181 	},
182 };
183 
184 struct platform_device tegra_spi_device2 = {
185 	.name		= "spi_tegra",
186 	.id		= 1,
187 	.resource	= spi_resource2,
188 	.num_resources	= ARRAY_SIZE(spi_resource2),
189 	.dev		= {
190 		.coherent_dma_mask	= 0xffffffff,
191 	},
192 };
193 
194 struct platform_device tegra_spi_device3 = {
195 	.name		= "spi_tegra",
196 	.id		= 2,
197 	.resource	= spi_resource3,
198 	.num_resources	= ARRAY_SIZE(spi_resource3),
199 	.dev		= {
200 		.coherent_dma_mask	= 0xffffffff,
201 	},
202 };
203 
204 struct platform_device tegra_spi_device4 = {
205 	.name		= "spi_tegra",
206 	.id		= 3,
207 	.resource	= spi_resource4,
208 	.num_resources	= ARRAY_SIZE(spi_resource4),
209 	.dev		= {
210 		.coherent_dma_mask	= 0xffffffff,
211 	},
212 };
213 
214 
215 static struct resource sdhci_resource1[] = {
216 	[0] = {
217 		.start	= INT_SDMMC1,
218 		.end	= INT_SDMMC1,
219 		.flags	= IORESOURCE_IRQ,
220 	},
221 	[1] = {
222 		.start	= TEGRA_SDMMC1_BASE,
223 		.end	= TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
224 		.flags	= IORESOURCE_MEM,
225 	},
226 };
227 
228 static struct resource sdhci_resource2[] = {
229 	[0] = {
230 		.start	= INT_SDMMC2,
231 		.end	= INT_SDMMC2,
232 		.flags	= IORESOURCE_IRQ,
233 	},
234 	[1] = {
235 		.start	= TEGRA_SDMMC2_BASE,
236 		.end	= TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
237 		.flags	= IORESOURCE_MEM,
238 	},
239 };
240 
241 static struct resource sdhci_resource3[] = {
242 	[0] = {
243 		.start	= INT_SDMMC3,
244 		.end	= INT_SDMMC3,
245 		.flags	= IORESOURCE_IRQ,
246 	},
247 	[1] = {
248 		.start	= TEGRA_SDMMC3_BASE,
249 		.end	= TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
250 		.flags	= IORESOURCE_MEM,
251 	},
252 };
253 
254 static struct resource sdhci_resource4[] = {
255 	[0] = {
256 		.start	= INT_SDMMC4,
257 		.end	= INT_SDMMC4,
258 		.flags	= IORESOURCE_IRQ,
259 	},
260 	[1] = {
261 		.start	= TEGRA_SDMMC4_BASE,
262 		.end	= TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
263 		.flags	= IORESOURCE_MEM,
264 	},
265 };
266 
267 /* board files should fill in platform_data register the devices themselvs.
268  * See board-harmony.c for an example
269  */
270 struct platform_device tegra_sdhci_device1 = {
271 	.name		= "sdhci-tegra",
272 	.id		= 0,
273 	.resource	= sdhci_resource1,
274 	.num_resources	= ARRAY_SIZE(sdhci_resource1),
275 };
276 
277 struct platform_device tegra_sdhci_device2 = {
278 	.name		= "sdhci-tegra",
279 	.id		= 1,
280 	.resource	= sdhci_resource2,
281 	.num_resources	= ARRAY_SIZE(sdhci_resource2),
282 };
283 
284 struct platform_device tegra_sdhci_device3 = {
285 	.name		= "sdhci-tegra",
286 	.id		= 2,
287 	.resource	= sdhci_resource3,
288 	.num_resources	= ARRAY_SIZE(sdhci_resource3),
289 };
290 
291 struct platform_device tegra_sdhci_device4 = {
292 	.name		= "sdhci-tegra",
293 	.id		= 3,
294 	.resource	= sdhci_resource4,
295 	.num_resources	= ARRAY_SIZE(sdhci_resource4),
296 };
297 
298 static struct resource tegra_usb1_resources[] = {
299 	[0] = {
300 		.start	= TEGRA_USB_BASE,
301 		.end	= TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
302 		.flags	= IORESOURCE_MEM,
303 	},
304 	[1] = {
305 		.start	= INT_USB,
306 		.end	= INT_USB,
307 		.flags	= IORESOURCE_IRQ,
308 	},
309 };
310 
311 static struct resource tegra_usb2_resources[] = {
312 	[0] = {
313 		.start	= TEGRA_USB2_BASE,
314 		.end	= TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
315 		.flags	= IORESOURCE_MEM,
316 	},
317 	[1] = {
318 		.start	= INT_USB2,
319 		.end	= INT_USB2,
320 		.flags	= IORESOURCE_IRQ,
321 	},
322 };
323 
324 static struct resource tegra_usb3_resources[] = {
325 	[0] = {
326 		.start	= TEGRA_USB3_BASE,
327 		.end	= TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
328 		.flags	= IORESOURCE_MEM,
329 	},
330 	[1] = {
331 		.start	= INT_USB3,
332 		.end	= INT_USB3,
333 		.flags	= IORESOURCE_IRQ,
334 	},
335 };
336 
337 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
338 
339 struct platform_device tegra_ehci1_device = {
340 	.name	= "tegra-ehci",
341 	.id	= 0,
342 	.dev	= {
343 		.dma_mask	= &tegra_ehci_dmamask,
344 		.coherent_dma_mask = DMA_BIT_MASK(32),
345 	},
346 	.resource = tegra_usb1_resources,
347 	.num_resources = ARRAY_SIZE(tegra_usb1_resources),
348 };
349 
350 struct platform_device tegra_ehci2_device = {
351 	.name	= "tegra-ehci",
352 	.id	= 1,
353 	.dev	= {
354 		.dma_mask	= &tegra_ehci_dmamask,
355 		.coherent_dma_mask = DMA_BIT_MASK(32),
356 	},
357 	.resource = tegra_usb2_resources,
358 	.num_resources = ARRAY_SIZE(tegra_usb2_resources),
359 };
360 
361 struct platform_device tegra_ehci3_device = {
362 	.name	= "tegra-ehci",
363 	.id	= 2,
364 	.dev	= {
365 		.dma_mask	= &tegra_ehci_dmamask,
366 		.coherent_dma_mask = DMA_BIT_MASK(32),
367 	},
368 	.resource = tegra_usb3_resources,
369 	.num_resources = ARRAY_SIZE(tegra_usb3_resources),
370 };
371 
372 static struct resource tegra_pmu_resources[] = {
373 	[0] = {
374 		.start	= INT_CPU0_PMU_INTR,
375 		.end	= INT_CPU0_PMU_INTR,
376 		.flags	= IORESOURCE_IRQ,
377 	},
378 	[1] = {
379 		.start	= INT_CPU1_PMU_INTR,
380 		.end	= INT_CPU1_PMU_INTR,
381 		.flags	= IORESOURCE_IRQ,
382 	},
383 };
384 
385 struct platform_device tegra_pmu_device = {
386 	.name		= "arm-pmu",
387 	.id		= ARM_PMU_DEVICE_CPU,
388 	.num_resources	= ARRAY_SIZE(tegra_pmu_resources),
389 	.resource	= tegra_pmu_resources,
390 };
391 
392 static struct resource tegra_uarta_resources[] = {
393 	[0] = {
394 		.start	= TEGRA_UARTA_BASE,
395 		.end	= TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
396 		.flags	= IORESOURCE_MEM,
397 	},
398 	[1] = {
399 		.start	= INT_UARTA,
400 		.end	= INT_UARTA,
401 		.flags	= IORESOURCE_IRQ,
402 	},
403 };
404 
405 static struct resource tegra_uartb_resources[] = {
406 	[0] = {
407 		.start	= TEGRA_UARTB_BASE,
408 		.end	= TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
409 		.flags	= IORESOURCE_MEM,
410 	},
411 	[1] = {
412 		.start	= INT_UARTB,
413 		.end	= INT_UARTB,
414 		.flags	= IORESOURCE_IRQ,
415 	},
416 };
417 
418 static struct resource tegra_uartc_resources[] = {
419 	[0] = {
420 		.start	= TEGRA_UARTC_BASE,
421 		.end	= TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
422 		.flags	= IORESOURCE_MEM,
423 	},
424 	[1] = {
425 		.start	= INT_UARTC,
426 		.end	= INT_UARTC,
427 		.flags	= IORESOURCE_IRQ,
428 	},
429 };
430 
431 static struct resource tegra_uartd_resources[] = {
432 	[0] = {
433 		.start	= TEGRA_UARTD_BASE,
434 		.end	= TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
435 		.flags	= IORESOURCE_MEM,
436 	},
437 	[1] = {
438 		.start	= INT_UARTD,
439 		.end	= INT_UARTD,
440 		.flags	= IORESOURCE_IRQ,
441 	},
442 };
443 
444 static struct resource tegra_uarte_resources[] = {
445 	[0] = {
446 		.start	= TEGRA_UARTE_BASE,
447 		.end	= TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
448 		.flags	= IORESOURCE_MEM,
449 	},
450 	[1] = {
451 		.start	= INT_UARTE,
452 		.end	= INT_UARTE,
453 		.flags	= IORESOURCE_IRQ,
454 	},
455 };
456 
457 struct platform_device tegra_uarta_device = {
458 	.name	= "tegra_uart",
459 	.id	= 0,
460 	.num_resources	= ARRAY_SIZE(tegra_uarta_resources),
461 	.resource	= tegra_uarta_resources,
462 	.dev	= {
463 		.coherent_dma_mask	= DMA_BIT_MASK(32),
464 	},
465 };
466 
467 struct platform_device tegra_uartb_device = {
468 	.name	= "tegra_uart",
469 	.id	= 1,
470 	.num_resources	= ARRAY_SIZE(tegra_uartb_resources),
471 	.resource	= tegra_uartb_resources,
472 	.dev	= {
473 		.coherent_dma_mask	= DMA_BIT_MASK(32),
474 	},
475 };
476 
477 struct platform_device tegra_uartc_device = {
478 	.name	= "tegra_uart",
479 	.id	= 2,
480 	.num_resources	= ARRAY_SIZE(tegra_uartc_resources),
481 	.resource	= tegra_uartc_resources,
482 	.dev	= {
483 		.coherent_dma_mask	= DMA_BIT_MASK(32),
484 	},
485 };
486 
487 struct platform_device tegra_uartd_device = {
488 	.name	= "tegra_uart",
489 	.id	= 3,
490 	.num_resources	= ARRAY_SIZE(tegra_uartd_resources),
491 	.resource	= tegra_uartd_resources,
492 	.dev	= {
493 		.coherent_dma_mask	= DMA_BIT_MASK(32),
494 	},
495 };
496 
497 struct platform_device tegra_uarte_device = {
498 	.name	= "tegra_uart",
499 	.id	= 4,
500 	.num_resources	= ARRAY_SIZE(tegra_uarte_resources),
501 	.resource	= tegra_uarte_resources,
502 	.dev	= {
503 		.coherent_dma_mask	= DMA_BIT_MASK(32),
504 	},
505 };
506 
507 static struct resource i2s_resource1[] = {
508 	[0] = {
509 		.start	= INT_I2S1,
510 		.end	= INT_I2S1,
511 		.flags	= IORESOURCE_IRQ
512 	},
513 	[1] = {
514 		.start	= TEGRA_DMA_REQ_SEL_I2S_1,
515 		.end	= TEGRA_DMA_REQ_SEL_I2S_1,
516 		.flags	= IORESOURCE_DMA
517 	},
518 	[2] = {
519 		.start	= TEGRA_I2S1_BASE,
520 		.end	= TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
521 		.flags	= IORESOURCE_MEM
522 	}
523 };
524 
525 static struct resource i2s_resource2[] = {
526 	[0] = {
527 		.start	= INT_I2S2,
528 		.end	= INT_I2S2,
529 		.flags	= IORESOURCE_IRQ
530 	},
531 	[1] = {
532 		.start	= TEGRA_DMA_REQ_SEL_I2S2_1,
533 		.end	= TEGRA_DMA_REQ_SEL_I2S2_1,
534 		.flags	= IORESOURCE_DMA
535 	},
536 	[2] = {
537 		.start	= TEGRA_I2S2_BASE,
538 		.end	= TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
539 		.flags	= IORESOURCE_MEM
540 	}
541 };
542 
543 struct platform_device tegra_i2s_device1 = {
544 	.name		= "tegra-i2s",
545 	.id		= 0,
546 	.resource	= i2s_resource1,
547 	.num_resources	= ARRAY_SIZE(i2s_resource1),
548 };
549 
550 struct platform_device tegra_i2s_device2 = {
551 	.name		= "tegra-i2s",
552 	.id		= 1,
553 	.resource	= i2s_resource2,
554 	.num_resources	= ARRAY_SIZE(i2s_resource2),
555 };
556 
557 static struct resource tegra_das_resources[] = {
558 	[0] = {
559 		.start = TEGRA_APB_MISC_DAS_BASE,
560 		.end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
561 		.flags = IORESOURCE_MEM,
562 	},
563 };
564 
565 struct platform_device tegra_das_device = {
566 	.name		= "tegra-das",
567 	.id		= -1,
568 	.num_resources	= ARRAY_SIZE(tegra_das_resources),
569 	.resource	= tegra_das_resources,
570 };
571 
572 struct platform_device tegra_pcm_device = {
573 	.name = "tegra-pcm-audio",
574 	.id = -1,
575 };
576