1 /* 2 * stmp378x: SSP register definitions 3 * 4 * Copyright (c) 2008 Freescale Semiconductor 5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000) 22 #define REGS_SSP1_PHYS 0x80010000 23 #define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000) 24 #define REGS_SSP2_PHYS 0x80034000 25 #define REGS_SSP_SIZE 0x2000 26 27 #define HW_SSP_CTRL0 0x0 28 #define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF 29 #define BP_SSP_CTRL0_XFER_COUNT 0 30 #define BM_SSP_CTRL0_ENABLE 0x00010000 31 #define BM_SSP_CTRL0_GET_RESP 0x00020000 32 #define BM_SSP_CTRL0_LONG_RESP 0x00080000 33 #define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 34 #define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 35 #define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 36 #define BP_SSP_CTRL0_BUS_WIDTH 22 37 #define BM_SSP_CTRL0_DATA_XFER 0x01000000 38 #define BM_SSP_CTRL0_READ 0x02000000 39 #define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 40 #define BM_SSP_CTRL0_LOCK_CS 0x08000000 41 #define BM_SSP_CTRL0_RUN 0x20000000 42 #define BM_SSP_CTRL0_CLKGATE 0x40000000 43 #define BM_SSP_CTRL0_SFTRST 0x80000000 44 45 #define HW_SSP_CMD0 0x10 46 #define BM_SSP_CMD0_CMD 0x000000FF 47 #define BP_SSP_CMD0_CMD 0 48 #define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 49 #define BP_SSP_CMD0_BLOCK_COUNT 8 50 #define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 51 #define BP_SSP_CMD0_BLOCK_SIZE 16 52 #define BM_SSP_CMD0_APPEND_8CYC 0x00100000 53 #define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF 54 #define BP_SSP_CMD1_CMD_ARG 0 55 56 #define HW_SSP_TIMING 0x50 57 #define BM_SSP_TIMING_CLOCK_RATE 0x000000FF 58 #define BP_SSP_TIMING_CLOCK_RATE 0 59 #define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 60 #define BP_SSP_TIMING_CLOCK_DIVIDE 8 61 #define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 62 #define BP_SSP_TIMING_TIMEOUT 16 63 64 #define HW_SSP_CTRL1 0x60 65 #define BM_SSP_CTRL1_SSP_MODE 0x0000000F 66 #define BP_SSP_CTRL1_SSP_MODE 0 67 #define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 68 #define BP_SSP_CTRL1_WORD_LENGTH 4 69 #define BM_SSP_CTRL1_POLARITY 0x00000200 70 #define BM_SSP_CTRL1_PHASE 0x00000400 71 #define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 72 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 73 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 74 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 75 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 76 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 77 #define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 78 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 79 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 80 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 81 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 82 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 83 #define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 84 #define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 85 86 #define HW_SSP_DATA 0x70 87 88 #define HW_SSP_SDRESP0 0x80 89 90 #define HW_SSP_SDRESP1 0x90 91 92 #define HW_SSP_SDRESP2 0xA0 93 94 #define HW_SSP_SDRESP3 0xB0 95 96 #define HW_SSP_STATUS 0xC0 97 #define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 98 #define BM_SSP_STATUS_TIMEOUT 0x00001000 99 #define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 100 #define BM_SSP_STATUS_RESP_ERR 0x00008000 101 #define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 102 #define BM_SSP_STATUS_CARD_DETECT 0x10000000 103