1 /* 2 * stmp378x: CLKCTRL register definitions 3 * 4 * Copyright (c) 2008 Freescale Semiconductor 5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #ifndef _MACH_REGS_CLKCTRL 22 #define _MACH_REGS_CLKCTRL 23 24 #define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) 25 #define REGS_CLKCTRL_PHYS 0x80040000 26 #define REGS_CLKCTRL_SIZE 0x2000 27 28 #define HW_CLKCTRL_PLLCTRL0 0x0 29 #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 30 31 #define HW_CLKCTRL_CPU 0x20 32 #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 33 #define BP_CLKCTRL_CPU_DIV_CPU 0 34 35 #define HW_CLKCTRL_HBUS 0x30 36 #define BM_CLKCTRL_HBUS_DIV 0x0000001F 37 #define BP_CLKCTRL_HBUS_DIV 0 38 #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 39 40 #define HW_CLKCTRL_XBUS 0x40 41 42 #define HW_CLKCTRL_XTAL 0x50 43 #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 44 45 #define HW_CLKCTRL_PIX 0x60 46 #define BM_CLKCTRL_PIX_DIV 0x00000FFF 47 #define BP_CLKCTRL_PIX_DIV 0 48 #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 49 50 #define HW_CLKCTRL_SSP 0x70 51 52 #define HW_CLKCTRL_GPMI 0x80 53 54 #define HW_CLKCTRL_SPDIF 0x90 55 56 #define HW_CLKCTRL_EMI 0xA0 57 #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F 58 #define BP_CLKCTRL_EMI_DIV_EMI 0 59 #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 60 #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 61 #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 62 #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 63 64 #define HW_CLKCTRL_IR 0xB0 65 66 #define HW_CLKCTRL_SAIF 0xC0 67 68 #define HW_CLKCTRL_TV 0xD0 69 70 #define HW_CLKCTRL_ETM 0xE0 71 72 #define HW_CLKCTRL_FRAC 0xF0 73 #define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 74 #define BP_CLKCTRL_FRAC_EMIFRAC 8 75 #define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 76 #define BP_CLKCTRL_FRAC_PIXFRAC 16 77 #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 78 79 #define HW_CLKCTRL_FRAC1 0x100 80 81 #define HW_CLKCTRL_CLKSEQ 0x110 82 #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 83 84 #define HW_CLKCTRL_RESET 0x120 85 #define BM_CLKCTRL_RESET_DIG 0x00000001 86 #define BP_CLKCTRL_RESET_DIG 0 87 88 #endif 89