1 /*
2 * arch/arm/mach-spear6xx/clock.c
3 *
4 * SPEAr6xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <plat/clock.h>
17 #include <mach/misc_regs.h>
18
19 /* root clks */
20 /* 32 KHz oscillator clock */
21 static struct clk osc_32k_clk = {
22 .flags = ALWAYS_ENABLED,
23 .rate = 32000,
24 };
25
26 /* 30 MHz oscillator clock */
27 static struct clk osc_30m_clk = {
28 .flags = ALWAYS_ENABLED,
29 .rate = 30000000,
30 };
31
32 /* clock derived from 32 KHz osc clk */
33 /* rtc clock */
34 static struct clk rtc_clk = {
35 .pclk = &osc_32k_clk,
36 .en_reg = PERIP1_CLK_ENB,
37 .en_reg_bit = RTC_CLK_ENB,
38 .recalc = &follow_parent,
39 };
40
41 /* clock derived from 30 MHz osc clk */
42 /* pll masks structure */
43 static struct pll_clk_masks pll1_masks = {
44 .mode_mask = PLL_MODE_MASK,
45 .mode_shift = PLL_MODE_SHIFT,
46 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
47 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
48 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
49 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
50 .div_p_mask = PLL_DIV_P_MASK,
51 .div_p_shift = PLL_DIV_P_SHIFT,
52 .div_n_mask = PLL_DIV_N_MASK,
53 .div_n_shift = PLL_DIV_N_SHIFT,
54 };
55
56 /* pll1 configuration structure */
57 static struct pll_clk_config pll1_config = {
58 .mode_reg = PLL1_CTR,
59 .cfg_reg = PLL1_FRQ,
60 .masks = &pll1_masks,
61 };
62
63 /* pll rate configuration table, in ascending order of rates */
64 struct pll_rate_tbl pll_rtbl[] = {
65 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
66 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
67 };
68
69 /* PLL1 clock */
70 static struct clk pll1_clk = {
71 .flags = ENABLED_ON_INIT,
72 .pclk = &osc_30m_clk,
73 .en_reg = PLL1_CTR,
74 .en_reg_bit = PLL_ENABLE,
75 .calc_rate = &pll_calc_rate,
76 .recalc = &pll_clk_recalc,
77 .set_rate = &pll_clk_set_rate,
78 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
79 .private_data = &pll1_config,
80 };
81
82 /* PLL3 48 MHz clock */
83 static struct clk pll3_48m_clk = {
84 .flags = ALWAYS_ENABLED,
85 .pclk = &osc_30m_clk,
86 .rate = 48000000,
87 };
88
89 /* watch dog timer clock */
90 static struct clk wdt_clk = {
91 .flags = ALWAYS_ENABLED,
92 .pclk = &osc_30m_clk,
93 .recalc = &follow_parent,
94 };
95
96 /* clock derived from pll1 clk */
97 /* cpu clock */
98 static struct clk cpu_clk = {
99 .flags = ALWAYS_ENABLED,
100 .pclk = &pll1_clk,
101 .recalc = &follow_parent,
102 };
103
104 /* ahb masks structure */
105 static struct bus_clk_masks ahb_masks = {
106 .mask = PLL_HCLK_RATIO_MASK,
107 .shift = PLL_HCLK_RATIO_SHIFT,
108 };
109
110 /* ahb configuration structure */
111 static struct bus_clk_config ahb_config = {
112 .reg = CORE_CLK_CFG,
113 .masks = &ahb_masks,
114 };
115
116 /* ahb rate configuration table, in ascending order of rates */
117 struct bus_rate_tbl bus_rtbl[] = {
118 {.div = 3}, /* == parent divided by 4 */
119 {.div = 2}, /* == parent divided by 3 */
120 {.div = 1}, /* == parent divided by 2 */
121 {.div = 0}, /* == parent divided by 1 */
122 };
123
124 /* ahb clock */
125 static struct clk ahb_clk = {
126 .flags = ALWAYS_ENABLED,
127 .pclk = &pll1_clk,
128 .calc_rate = &bus_calc_rate,
129 .recalc = &bus_clk_recalc,
130 .set_rate = &bus_clk_set_rate,
131 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
132 .private_data = &ahb_config,
133 };
134
135 /* auxiliary synthesizers masks */
136 static struct aux_clk_masks aux_masks = {
137 .eq_sel_mask = AUX_EQ_SEL_MASK,
138 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
139 .eq1_mask = AUX_EQ1_SEL,
140 .eq2_mask = AUX_EQ2_SEL,
141 .xscale_sel_mask = AUX_XSCALE_MASK,
142 .xscale_sel_shift = AUX_XSCALE_SHIFT,
143 .yscale_sel_mask = AUX_YSCALE_MASK,
144 .yscale_sel_shift = AUX_YSCALE_SHIFT,
145 };
146
147 /* uart configurations */
148 static struct aux_clk_config uart_synth_config = {
149 .synth_reg = UART_CLK_SYNT,
150 .masks = &aux_masks,
151 };
152
153 /* aux rate configuration table, in ascending order of rates */
154 struct aux_rate_tbl aux_rtbl[] = {
155 /* For PLL1 = 332 MHz */
156 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
157 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
158 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
159 };
160
161 /* uart synth clock */
162 static struct clk uart_synth_clk = {
163 .en_reg = UART_CLK_SYNT,
164 .en_reg_bit = AUX_SYNT_ENB,
165 .pclk = &pll1_clk,
166 .calc_rate = &aux_calc_rate,
167 .recalc = &aux_clk_recalc,
168 .set_rate = &aux_clk_set_rate,
169 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
170 .private_data = &uart_synth_config,
171 };
172
173 /* uart parents */
174 static struct pclk_info uart_pclk_info[] = {
175 {
176 .pclk = &uart_synth_clk,
177 .pclk_val = AUX_CLK_PLL1_VAL,
178 }, {
179 .pclk = &pll3_48m_clk,
180 .pclk_val = AUX_CLK_PLL3_VAL,
181 },
182 };
183
184 /* uart parent select structure */
185 static struct pclk_sel uart_pclk_sel = {
186 .pclk_info = uart_pclk_info,
187 .pclk_count = ARRAY_SIZE(uart_pclk_info),
188 .pclk_sel_reg = PERIP_CLK_CFG,
189 .pclk_sel_mask = UART_CLK_MASK,
190 };
191
192 /* uart0 clock */
193 static struct clk uart0_clk = {
194 .en_reg = PERIP1_CLK_ENB,
195 .en_reg_bit = UART0_CLK_ENB,
196 .pclk_sel = &uart_pclk_sel,
197 .pclk_sel_shift = UART_CLK_SHIFT,
198 .recalc = &follow_parent,
199 };
200
201 /* uart1 clock */
202 static struct clk uart1_clk = {
203 .en_reg = PERIP1_CLK_ENB,
204 .en_reg_bit = UART1_CLK_ENB,
205 .pclk_sel = &uart_pclk_sel,
206 .pclk_sel_shift = UART_CLK_SHIFT,
207 .recalc = &follow_parent,
208 };
209
210 /* firda configurations */
211 static struct aux_clk_config firda_synth_config = {
212 .synth_reg = FIRDA_CLK_SYNT,
213 .masks = &aux_masks,
214 };
215
216 /* firda synth clock */
217 static struct clk firda_synth_clk = {
218 .en_reg = FIRDA_CLK_SYNT,
219 .en_reg_bit = AUX_SYNT_ENB,
220 .pclk = &pll1_clk,
221 .calc_rate = &aux_calc_rate,
222 .recalc = &aux_clk_recalc,
223 .set_rate = &aux_clk_set_rate,
224 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
225 .private_data = &firda_synth_config,
226 };
227
228 /* firda parents */
229 static struct pclk_info firda_pclk_info[] = {
230 {
231 .pclk = &firda_synth_clk,
232 .pclk_val = AUX_CLK_PLL1_VAL,
233 }, {
234 .pclk = &pll3_48m_clk,
235 .pclk_val = AUX_CLK_PLL3_VAL,
236 },
237 };
238
239 /* firda parent select structure */
240 static struct pclk_sel firda_pclk_sel = {
241 .pclk_info = firda_pclk_info,
242 .pclk_count = ARRAY_SIZE(firda_pclk_info),
243 .pclk_sel_reg = PERIP_CLK_CFG,
244 .pclk_sel_mask = FIRDA_CLK_MASK,
245 };
246
247 /* firda clock */
248 static struct clk firda_clk = {
249 .en_reg = PERIP1_CLK_ENB,
250 .en_reg_bit = FIRDA_CLK_ENB,
251 .pclk_sel = &firda_pclk_sel,
252 .pclk_sel_shift = FIRDA_CLK_SHIFT,
253 .recalc = &follow_parent,
254 };
255
256 /* clcd configurations */
257 static struct aux_clk_config clcd_synth_config = {
258 .synth_reg = CLCD_CLK_SYNT,
259 .masks = &aux_masks,
260 };
261
262 /* firda synth clock */
263 static struct clk clcd_synth_clk = {
264 .en_reg = CLCD_CLK_SYNT,
265 .en_reg_bit = AUX_SYNT_ENB,
266 .pclk = &pll1_clk,
267 .calc_rate = &aux_calc_rate,
268 .recalc = &aux_clk_recalc,
269 .set_rate = &aux_clk_set_rate,
270 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
271 .private_data = &clcd_synth_config,
272 };
273
274 /* clcd parents */
275 static struct pclk_info clcd_pclk_info[] = {
276 {
277 .pclk = &clcd_synth_clk,
278 .pclk_val = AUX_CLK_PLL1_VAL,
279 }, {
280 .pclk = &pll3_48m_clk,
281 .pclk_val = AUX_CLK_PLL3_VAL,
282 },
283 };
284
285 /* clcd parent select structure */
286 static struct pclk_sel clcd_pclk_sel = {
287 .pclk_info = clcd_pclk_info,
288 .pclk_count = ARRAY_SIZE(clcd_pclk_info),
289 .pclk_sel_reg = PERIP_CLK_CFG,
290 .pclk_sel_mask = CLCD_CLK_MASK,
291 };
292
293 /* clcd clock */
294 static struct clk clcd_clk = {
295 .en_reg = PERIP1_CLK_ENB,
296 .en_reg_bit = CLCD_CLK_ENB,
297 .pclk_sel = &clcd_pclk_sel,
298 .pclk_sel_shift = CLCD_CLK_SHIFT,
299 .recalc = &follow_parent,
300 };
301
302 /* gpt synthesizer masks */
303 static struct gpt_clk_masks gpt_masks = {
304 .mscale_sel_mask = GPT_MSCALE_MASK,
305 .mscale_sel_shift = GPT_MSCALE_SHIFT,
306 .nscale_sel_mask = GPT_NSCALE_MASK,
307 .nscale_sel_shift = GPT_NSCALE_SHIFT,
308 };
309
310 /* gpt rate configuration table, in ascending order of rates */
311 struct gpt_rate_tbl gpt_rtbl[] = {
312 /* For pll1 = 332 MHz */
313 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
314 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
315 {.mscale = 1, .nscale = 0}, /* 83 MHz */
316 };
317
318 /* gpt0 synth clk config*/
319 static struct gpt_clk_config gpt0_synth_config = {
320 .synth_reg = PRSC1_CLK_CFG,
321 .masks = &gpt_masks,
322 };
323
324 /* gpt synth clock */
325 static struct clk gpt0_synth_clk = {
326 .flags = ALWAYS_ENABLED,
327 .pclk = &pll1_clk,
328 .calc_rate = &gpt_calc_rate,
329 .recalc = &gpt_clk_recalc,
330 .set_rate = &gpt_clk_set_rate,
331 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
332 .private_data = &gpt0_synth_config,
333 };
334
335 /* gpt parents */
336 static struct pclk_info gpt0_pclk_info[] = {
337 {
338 .pclk = &gpt0_synth_clk,
339 .pclk_val = AUX_CLK_PLL1_VAL,
340 }, {
341 .pclk = &pll3_48m_clk,
342 .pclk_val = AUX_CLK_PLL3_VAL,
343 },
344 };
345
346 /* gpt parent select structure */
347 static struct pclk_sel gpt0_pclk_sel = {
348 .pclk_info = gpt0_pclk_info,
349 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
350 .pclk_sel_reg = PERIP_CLK_CFG,
351 .pclk_sel_mask = GPT_CLK_MASK,
352 };
353
354 /* gpt0 ARM1 subsystem timer clock */
355 static struct clk gpt0_clk = {
356 .flags = ALWAYS_ENABLED,
357 .pclk_sel = &gpt0_pclk_sel,
358 .pclk_sel_shift = GPT0_CLK_SHIFT,
359 .recalc = &follow_parent,
360 };
361
362
363 /* Note: gpt0 and gpt1 share same parent clocks */
364 /* gpt parent select structure */
365 static struct pclk_sel gpt1_pclk_sel = {
366 .pclk_info = gpt0_pclk_info,
367 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
368 .pclk_sel_reg = PERIP_CLK_CFG,
369 .pclk_sel_mask = GPT_CLK_MASK,
370 };
371
372 /* gpt1 timer clock */
373 static struct clk gpt1_clk = {
374 .flags = ALWAYS_ENABLED,
375 .pclk_sel = &gpt1_pclk_sel,
376 .pclk_sel_shift = GPT1_CLK_SHIFT,
377 .recalc = &follow_parent,
378 };
379
380 /* gpt2 synth clk config*/
381 static struct gpt_clk_config gpt2_synth_config = {
382 .synth_reg = PRSC2_CLK_CFG,
383 .masks = &gpt_masks,
384 };
385
386 /* gpt synth clock */
387 static struct clk gpt2_synth_clk = {
388 .flags = ALWAYS_ENABLED,
389 .pclk = &pll1_clk,
390 .calc_rate = &gpt_calc_rate,
391 .recalc = &gpt_clk_recalc,
392 .set_rate = &gpt_clk_set_rate,
393 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
394 .private_data = &gpt2_synth_config,
395 };
396
397 /* gpt parents */
398 static struct pclk_info gpt2_pclk_info[] = {
399 {
400 .pclk = &gpt2_synth_clk,
401 .pclk_val = AUX_CLK_PLL1_VAL,
402 }, {
403 .pclk = &pll3_48m_clk,
404 .pclk_val = AUX_CLK_PLL3_VAL,
405 },
406 };
407
408 /* gpt parent select structure */
409 static struct pclk_sel gpt2_pclk_sel = {
410 .pclk_info = gpt2_pclk_info,
411 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
412 .pclk_sel_reg = PERIP_CLK_CFG,
413 .pclk_sel_mask = GPT_CLK_MASK,
414 };
415
416 /* gpt2 timer clock */
417 static struct clk gpt2_clk = {
418 .flags = ALWAYS_ENABLED,
419 .pclk_sel = &gpt2_pclk_sel,
420 .pclk_sel_shift = GPT2_CLK_SHIFT,
421 .recalc = &follow_parent,
422 };
423
424 /* gpt3 synth clk config*/
425 static struct gpt_clk_config gpt3_synth_config = {
426 .synth_reg = PRSC3_CLK_CFG,
427 .masks = &gpt_masks,
428 };
429
430 /* gpt synth clock */
431 static struct clk gpt3_synth_clk = {
432 .flags = ALWAYS_ENABLED,
433 .pclk = &pll1_clk,
434 .calc_rate = &gpt_calc_rate,
435 .recalc = &gpt_clk_recalc,
436 .set_rate = &gpt_clk_set_rate,
437 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
438 .private_data = &gpt3_synth_config,
439 };
440
441 /* gpt parents */
442 static struct pclk_info gpt3_pclk_info[] = {
443 {
444 .pclk = &gpt3_synth_clk,
445 .pclk_val = AUX_CLK_PLL1_VAL,
446 }, {
447 .pclk = &pll3_48m_clk,
448 .pclk_val = AUX_CLK_PLL3_VAL,
449 },
450 };
451
452 /* gpt parent select structure */
453 static struct pclk_sel gpt3_pclk_sel = {
454 .pclk_info = gpt3_pclk_info,
455 .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
456 .pclk_sel_reg = PERIP_CLK_CFG,
457 .pclk_sel_mask = GPT_CLK_MASK,
458 };
459
460 /* gpt3 timer clock */
461 static struct clk gpt3_clk = {
462 .flags = ALWAYS_ENABLED,
463 .pclk_sel = &gpt3_pclk_sel,
464 .pclk_sel_shift = GPT3_CLK_SHIFT,
465 .recalc = &follow_parent,
466 };
467
468 /* clock derived from pll3 clk */
469 /* usbh0 clock */
470 static struct clk usbh0_clk = {
471 .pclk = &pll3_48m_clk,
472 .en_reg = PERIP1_CLK_ENB,
473 .en_reg_bit = USBH0_CLK_ENB,
474 .recalc = &follow_parent,
475 };
476
477 /* usbh1 clock */
478 static struct clk usbh1_clk = {
479 .pclk = &pll3_48m_clk,
480 .en_reg = PERIP1_CLK_ENB,
481 .en_reg_bit = USBH1_CLK_ENB,
482 .recalc = &follow_parent,
483 };
484
485 /* usbd clock */
486 static struct clk usbd_clk = {
487 .pclk = &pll3_48m_clk,
488 .en_reg = PERIP1_CLK_ENB,
489 .en_reg_bit = USBD_CLK_ENB,
490 .recalc = &follow_parent,
491 };
492
493 /* clock derived from ahb clk */
494 /* apb masks structure */
495 static struct bus_clk_masks apb_masks = {
496 .mask = HCLK_PCLK_RATIO_MASK,
497 .shift = HCLK_PCLK_RATIO_SHIFT,
498 };
499
500 /* apb configuration structure */
501 static struct bus_clk_config apb_config = {
502 .reg = CORE_CLK_CFG,
503 .masks = &apb_masks,
504 };
505
506 /* apb clock */
507 static struct clk apb_clk = {
508 .flags = ALWAYS_ENABLED,
509 .pclk = &ahb_clk,
510 .calc_rate = &bus_calc_rate,
511 .recalc = &bus_clk_recalc,
512 .set_rate = &bus_clk_set_rate,
513 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
514 .private_data = &apb_config,
515 };
516
517 /* i2c clock */
518 static struct clk i2c_clk = {
519 .pclk = &ahb_clk,
520 .en_reg = PERIP1_CLK_ENB,
521 .en_reg_bit = I2C_CLK_ENB,
522 .recalc = &follow_parent,
523 };
524
525 /* dma clock */
526 static struct clk dma_clk = {
527 .pclk = &ahb_clk,
528 .en_reg = PERIP1_CLK_ENB,
529 .en_reg_bit = DMA_CLK_ENB,
530 .recalc = &follow_parent,
531 };
532
533 /* jpeg clock */
534 static struct clk jpeg_clk = {
535 .pclk = &ahb_clk,
536 .en_reg = PERIP1_CLK_ENB,
537 .en_reg_bit = JPEG_CLK_ENB,
538 .recalc = &follow_parent,
539 };
540
541 /* gmac clock */
542 static struct clk gmac_clk = {
543 .pclk = &ahb_clk,
544 .en_reg = PERIP1_CLK_ENB,
545 .en_reg_bit = GMAC_CLK_ENB,
546 .recalc = &follow_parent,
547 };
548
549 /* smi clock */
550 static struct clk smi_clk = {
551 .pclk = &ahb_clk,
552 .en_reg = PERIP1_CLK_ENB,
553 .en_reg_bit = SMI_CLK_ENB,
554 .recalc = &follow_parent,
555 };
556
557 /* fsmc clock */
558 static struct clk fsmc_clk = {
559 .pclk = &ahb_clk,
560 .en_reg = PERIP1_CLK_ENB,
561 .en_reg_bit = FSMC_CLK_ENB,
562 .recalc = &follow_parent,
563 };
564
565 /* clock derived from apb clk */
566 /* adc clock */
567 static struct clk adc_clk = {
568 .pclk = &apb_clk,
569 .en_reg = PERIP1_CLK_ENB,
570 .en_reg_bit = ADC_CLK_ENB,
571 .recalc = &follow_parent,
572 };
573
574 /* ssp0 clock */
575 static struct clk ssp0_clk = {
576 .pclk = &apb_clk,
577 .en_reg = PERIP1_CLK_ENB,
578 .en_reg_bit = SSP0_CLK_ENB,
579 .recalc = &follow_parent,
580 };
581
582 /* ssp1 clock */
583 static struct clk ssp1_clk = {
584 .pclk = &apb_clk,
585 .en_reg = PERIP1_CLK_ENB,
586 .en_reg_bit = SSP1_CLK_ENB,
587 .recalc = &follow_parent,
588 };
589
590 /* ssp2 clock */
591 static struct clk ssp2_clk = {
592 .pclk = &apb_clk,
593 .en_reg = PERIP1_CLK_ENB,
594 .en_reg_bit = SSP2_CLK_ENB,
595 .recalc = &follow_parent,
596 };
597
598 /* gpio0 ARM subsystem clock */
599 static struct clk gpio0_clk = {
600 .flags = ALWAYS_ENABLED,
601 .pclk = &apb_clk,
602 .recalc = &follow_parent,
603 };
604
605 /* gpio1 clock */
606 static struct clk gpio1_clk = {
607 .pclk = &apb_clk,
608 .en_reg = PERIP1_CLK_ENB,
609 .en_reg_bit = GPIO1_CLK_ENB,
610 .recalc = &follow_parent,
611 };
612
613 /* gpio2 clock */
614 static struct clk gpio2_clk = {
615 .pclk = &apb_clk,
616 .en_reg = PERIP1_CLK_ENB,
617 .en_reg_bit = GPIO2_CLK_ENB,
618 .recalc = &follow_parent,
619 };
620
621 static struct clk dummy_apb_pclk;
622
623 /* array of all spear 6xx clock lookups */
624 static struct clk_lookup spear_clk_lookups[] = {
625 { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
626 /* root clks */
627 { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
628 { .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
629 /* clock derived from 32 KHz os clk */
630 { .dev_id = "rtc-spear", .clk = &rtc_clk},
631 /* clock derived from 30 MHz os clk */
632 { .con_id = "pll1_clk", .clk = &pll1_clk},
633 { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
634 { .dev_id = "wdt", .clk = &wdt_clk},
635 /* clock derived from pll1 clk */
636 { .con_id = "cpu_clk", .clk = &cpu_clk},
637 { .con_id = "ahb_clk", .clk = &ahb_clk},
638 { .con_id = "uart_synth_clk", .clk = &uart_synth_clk},
639 { .con_id = "firda_synth_clk", .clk = &firda_synth_clk},
640 { .con_id = "clcd_synth_clk", .clk = &clcd_synth_clk},
641 { .con_id = "gpt0_synth_clk", .clk = &gpt0_synth_clk},
642 { .con_id = "gpt2_synth_clk", .clk = &gpt2_synth_clk},
643 { .con_id = "gpt3_synth_clk", .clk = &gpt3_synth_clk},
644 { .dev_id = "uart0", .clk = &uart0_clk},
645 { .dev_id = "uart1", .clk = &uart1_clk},
646 { .dev_id = "firda", .clk = &firda_clk},
647 { .dev_id = "clcd", .clk = &clcd_clk},
648 { .dev_id = "gpt0", .clk = &gpt0_clk},
649 { .dev_id = "gpt1", .clk = &gpt1_clk},
650 { .dev_id = "gpt2", .clk = &gpt2_clk},
651 { .dev_id = "gpt3", .clk = &gpt3_clk},
652 /* clock derived from pll3 clk */
653 { .dev_id = "designware_udc", .clk = &usbd_clk},
654 { .con_id = "usbh.0_clk", .clk = &usbh0_clk},
655 { .con_id = "usbh.1_clk", .clk = &usbh1_clk},
656 /* clock derived from ahb clk */
657 { .con_id = "apb_clk", .clk = &apb_clk},
658 { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
659 { .dev_id = "dma", .clk = &dma_clk},
660 { .dev_id = "jpeg", .clk = &jpeg_clk},
661 { .dev_id = "gmac", .clk = &gmac_clk},
662 { .dev_id = "smi", .clk = &smi_clk},
663 { .con_id = "fsmc", .clk = &fsmc_clk},
664 /* clock derived from apb clk */
665 { .dev_id = "adc", .clk = &adc_clk},
666 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
667 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
668 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
669 { .dev_id = "gpio0", .clk = &gpio0_clk},
670 { .dev_id = "gpio1", .clk = &gpio1_clk},
671 { .dev_id = "gpio2", .clk = &gpio2_clk},
672 };
673
clk_init(void)674 void __init clk_init(void)
675 {
676 int i;
677
678 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
679 clk_register(&spear_clk_lookups[i]);
680
681 recalc_root_clocks();
682 }
683