1 /* linux/arch/arm/plat-s3c64xx/pm.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX CPU PM support.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/suspend.h>
17 #include <linux/serial_core.h>
18 #include <linux/io.h>
19
20 #include <mach/map.h>
21 #include <mach/irqs.h>
22
23 #include <plat/pm.h>
24 #include <plat/wakeup-mask.h>
25
26 #include <mach/regs-sys.h>
27 #include <mach/regs-gpio.h>
28 #include <mach/regs-clock.h>
29 #include <mach/regs-syscon-power.h>
30 #include <mach/regs-gpio-memport.h>
31
32 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
33 #include <mach/gpio-bank-n.h>
34
s3c_pm_debug_smdkled(u32 set,u32 clear)35 void s3c_pm_debug_smdkled(u32 set, u32 clear)
36 {
37 unsigned long flags;
38 u32 reg;
39
40 local_irq_save(flags);
41 reg = __raw_readl(S3C64XX_GPNCON);
42 reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
43 S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
44 reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
45 S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
46 __raw_writel(reg, S3C64XX_GPNCON);
47
48 reg = __raw_readl(S3C64XX_GPNDAT);
49 reg &= ~(clear << 12);
50 reg |= set << 12;
51 __raw_writel(reg, S3C64XX_GPNDAT);
52
53 local_irq_restore(flags);
54 }
55 #endif
56
57 static struct sleep_save core_save[] = {
58 SAVE_ITEM(S3C_APLL_LOCK),
59 SAVE_ITEM(S3C_MPLL_LOCK),
60 SAVE_ITEM(S3C_EPLL_LOCK),
61 SAVE_ITEM(S3C_CLK_SRC),
62 SAVE_ITEM(S3C_CLK_DIV0),
63 SAVE_ITEM(S3C_CLK_DIV1),
64 SAVE_ITEM(S3C_CLK_DIV2),
65 SAVE_ITEM(S3C_CLK_OUT),
66 SAVE_ITEM(S3C_HCLK_GATE),
67 SAVE_ITEM(S3C_PCLK_GATE),
68 SAVE_ITEM(S3C_SCLK_GATE),
69 SAVE_ITEM(S3C_MEM0_GATE),
70
71 SAVE_ITEM(S3C_EPLL_CON1),
72 SAVE_ITEM(S3C_EPLL_CON0),
73
74 SAVE_ITEM(S3C64XX_MEM0DRVCON),
75 SAVE_ITEM(S3C64XX_MEM1DRVCON),
76
77 #ifndef CONFIG_CPU_FREQ
78 SAVE_ITEM(S3C_APLL_CON),
79 SAVE_ITEM(S3C_MPLL_CON),
80 #endif
81 };
82
83 static struct sleep_save misc_save[] = {
84 SAVE_ITEM(S3C64XX_AHB_CON0),
85 SAVE_ITEM(S3C64XX_AHB_CON1),
86 SAVE_ITEM(S3C64XX_AHB_CON2),
87
88 SAVE_ITEM(S3C64XX_SPCON),
89
90 SAVE_ITEM(S3C64XX_MEM0CONSTOP),
91 SAVE_ITEM(S3C64XX_MEM1CONSTOP),
92 SAVE_ITEM(S3C64XX_MEM0CONSLP0),
93 SAVE_ITEM(S3C64XX_MEM0CONSLP1),
94 SAVE_ITEM(S3C64XX_MEM1CONSLP),
95 };
96
s3c_pm_configure_extint(void)97 void s3c_pm_configure_extint(void)
98 {
99 __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
100 }
101
s3c_pm_restore_core(void)102 void s3c_pm_restore_core(void)
103 {
104 __raw_writel(0, S3C64XX_EINT_MASK);
105
106 s3c_pm_debug_smdkled(1 << 2, 0);
107
108 s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
109 s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
110 }
111
s3c_pm_save_core(void)112 void s3c_pm_save_core(void)
113 {
114 s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
115 s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
116 }
117
118 /* since both s3c6400 and s3c6410 share the same sleep pm calls, we
119 * put the per-cpu code in here until any new cpu comes along and changes
120 * this.
121 */
122
s3c64xx_cpu_suspend(void)123 static void s3c64xx_cpu_suspend(void)
124 {
125 unsigned long tmp;
126
127 /* set our standby method to sleep */
128
129 tmp = __raw_readl(S3C64XX_PWR_CFG);
130 tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
131 tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
132 __raw_writel(tmp, S3C64XX_PWR_CFG);
133
134 /* clear any old wakeup */
135
136 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
137 S3C64XX_WAKEUP_STAT);
138
139 /* set the LED state to 0110 over sleep */
140 s3c_pm_debug_smdkled(3 << 1, 0xf);
141
142 /* issue the standby signal into the pm unit. Note, we
143 * issue a write-buffer drain just in case */
144
145 tmp = 0;
146
147 asm("b 1f\n\t"
148 ".align 5\n\t"
149 "1:\n\t"
150 "mcr p15, 0, %0, c7, c10, 5\n\t"
151 "mcr p15, 0, %0, c7, c10, 4\n\t"
152 "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
153
154 /* we should never get past here */
155
156 panic("sleep resumed to originator?");
157 }
158
159 /* mapping of interrupts to parts of the wakeup mask */
160 static struct samsung_wakeup_mask wake_irqs[] = {
161 { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
162 { .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
163 { .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, },
164 { .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
165 { .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
166 { .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
167 { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
168 { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
169 { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
170 { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
171 };
172
s3c64xx_pm_prepare(void)173 static void s3c64xx_pm_prepare(void)
174 {
175 samsung_sync_wakemask(S3C64XX_PWR_CFG,
176 wake_irqs, ARRAY_SIZE(wake_irqs));
177
178 /* store address of resume. */
179 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
180
181 /* ensure previous wakeup state is cleared before sleeping */
182 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
183 }
184
s3c64xx_pm_init(void)185 static int s3c64xx_pm_init(void)
186 {
187 pm_cpu_prep = s3c64xx_pm_prepare;
188 pm_cpu_sleep = s3c64xx_cpu_suspend;
189 pm_uart_udivslot = 1;
190 return 0;
191 }
192
193 arch_initcall(s3c64xx_pm_init);
194