1 /* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/sysdev.h>
27 #include <linux/io.h>
28
29 #include <mach/hardware.h>
30 #include <asm/irq.h>
31
32 #include <asm/mach/irq.h>
33
34 #include <mach/regs-irq.h>
35 #include <mach/regs-gpio.h>
36
37 #include <plat/cpu.h>
38 #include <plat/pm.h>
39 #include <plat/irq.h>
40
41 /* camera irq */
42
s3c_irq_demux_cam(unsigned int irq,struct irq_desc * desc)43 static void s3c_irq_demux_cam(unsigned int irq,
44 struct irq_desc *desc)
45 {
46 unsigned int subsrc, submsk;
47
48 /* read the current pending interrupts, and the mask
49 * for what it is available */
50
51 subsrc = __raw_readl(S3C2410_SUBSRCPND);
52 submsk = __raw_readl(S3C2410_INTSUBMSK);
53
54 subsrc &= ~submsk;
55 subsrc >>= 11;
56 subsrc &= 3;
57
58 if (subsrc != 0) {
59 if (subsrc & 1) {
60 generic_handle_irq(IRQ_S3C2440_CAM_C);
61 }
62 if (subsrc & 2) {
63 generic_handle_irq(IRQ_S3C2440_CAM_P);
64 }
65 }
66 }
67
68 #define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
69
70 static void
s3c_irq_cam_mask(struct irq_data * data)71 s3c_irq_cam_mask(struct irq_data *data)
72 {
73 s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
74 }
75
76 static void
s3c_irq_cam_unmask(struct irq_data * data)77 s3c_irq_cam_unmask(struct irq_data *data)
78 {
79 s3c_irqsub_unmask(data->irq, INTMSK_CAM);
80 }
81
82 static void
s3c_irq_cam_ack(struct irq_data * data)83 s3c_irq_cam_ack(struct irq_data *data)
84 {
85 s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
86 }
87
88 static struct irq_chip s3c_irq_cam = {
89 .irq_mask = s3c_irq_cam_mask,
90 .irq_unmask = s3c_irq_cam_unmask,
91 .irq_ack = s3c_irq_cam_ack,
92 };
93
s3c244x_irq_add(struct sys_device * sysdev)94 static int s3c244x_irq_add(struct sys_device *sysdev)
95 {
96 unsigned int irqno;
97
98 irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
99 handle_level_irq);
100 set_irq_flags(IRQ_NFCON, IRQF_VALID);
101
102 /* add chained handler for camera */
103
104 irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
105 handle_level_irq);
106 irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
107
108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
109 irq_set_chip_and_handler(irqno, &s3c_irq_cam,
110 handle_level_irq);
111 set_irq_flags(irqno, IRQF_VALID);
112 }
113
114 return 0;
115 }
116
117 static struct sysdev_driver s3c2440_irq_driver = {
118 .add = s3c244x_irq_add,
119 .suspend = s3c24xx_irq_suspend,
120 .resume = s3c24xx_irq_resume,
121 };
122
s3c2440_irq_init(void)123 static int s3c2440_irq_init(void)
124 {
125 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
126 }
127
128 arch_initcall(s3c2440_irq_init);
129
130 static struct sysdev_driver s3c2442_irq_driver = {
131 .add = s3c244x_irq_add,
132 .suspend = s3c24xx_irq_suspend,
133 .resume = s3c24xx_irq_resume,
134 };
135
136
s3c2442_irq_init(void)137 static int s3c2442_irq_init(void)
138 {
139 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver);
140 }
141
142 arch_initcall(s3c2442_irq_init);
143