1 /*
2 * linux/arch/arm/mach-pxa/clock-pxa3xx.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/io.h>
13
14 #include <mach/smemc.h>
15 #include <mach/pxa3xx-regs.h>
16
17 #include "clock.h"
18
19 /* Crystal clock: 13MHz */
20 #define BASE_CLK 13000000
21
22 /* Ring Oscillator Clock: 60MHz */
23 #define RO_CLK 60000000
24
25 #define ACCR_D0CS (1 << 26)
26 #define ACCR_PCCE (1 << 11)
27
28 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
29 static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
30
31 /*
32 * Get the clock frequency as reflected by CCSR and the turbo flag.
33 * We assume these values have been applied via a fcs.
34 * If info is not 0 we also display the current settings.
35 */
pxa3xx_get_clk_frequency_khz(int info)36 unsigned int pxa3xx_get_clk_frequency_khz(int info)
37 {
38 unsigned long acsr, xclkcfg;
39 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
40
41 /* Read XCLKCFG register turbo bit */
42 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
43 t = xclkcfg & 0x1;
44
45 acsr = ACSR;
46
47 xl = acsr & 0x1f;
48 xn = (acsr >> 8) & 0x7;
49 hss = (acsr >> 14) & 0x3;
50
51 XL = xl * BASE_CLK;
52 XN = xn * XL;
53
54 ro = acsr & ACCR_D0CS;
55
56 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
57 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
58
59 if (info) {
60 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
61 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
62 (ro) ? "" : "in");
63 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
64 XL / 1000000, (XL % 1000000) / 10000, xl);
65 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
66 XN / 1000000, (XN % 1000000) / 10000, xn,
67 (t) ? "" : "in");
68 pr_info("HSIO bus clock: %d.%02dMHz\n",
69 HSS / 1000000, (HSS % 1000000) / 10000);
70 }
71
72 return CLK / 1000;
73 }
74
75 /*
76 * Return the current AC97 clock frequency.
77 */
clk_pxa3xx_ac97_getrate(struct clk * clk)78 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
79 {
80 unsigned long rate = 312000000;
81 unsigned long ac97_div;
82
83 ac97_div = AC97_DIV;
84
85 /* This may loose precision for some rates but won't for the
86 * standard 24.576MHz.
87 */
88 rate /= (ac97_div >> 12) & 0x7fff;
89 rate *= (ac97_div & 0xfff);
90
91 return rate;
92 }
93
94 /*
95 * Return the current HSIO bus clock frequency
96 */
clk_pxa3xx_hsio_getrate(struct clk * clk)97 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
98 {
99 unsigned long acsr;
100 unsigned int hss, hsio_clk;
101
102 acsr = ACSR;
103
104 hss = (acsr >> 14) & 0x3;
105 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
106
107 return hsio_clk;
108 }
109
110 /* crystal frequency to static memory controller multiplier (SMCFS) */
111 static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
112 static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
113
clk_pxa3xx_smemc_getrate(struct clk * clk)114 static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
115 {
116 unsigned long acsr = ACSR;
117 unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
118
119 return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
120 df_clkdiv[(memclkcfg >> 16) & 0x3];
121 }
122
clk_pxa3xx_cken_enable(struct clk * clk)123 void clk_pxa3xx_cken_enable(struct clk *clk)
124 {
125 unsigned long mask = 1ul << (clk->cken & 0x1f);
126
127 if (clk->cken < 32)
128 CKENA |= mask;
129 else
130 CKENB |= mask;
131 }
132
clk_pxa3xx_cken_disable(struct clk * clk)133 void clk_pxa3xx_cken_disable(struct clk *clk)
134 {
135 unsigned long mask = 1ul << (clk->cken & 0x1f);
136
137 if (clk->cken < 32)
138 CKENA &= ~mask;
139 else
140 CKENB &= ~mask;
141 }
142
143 const struct clkops clk_pxa3xx_cken_ops = {
144 .enable = clk_pxa3xx_cken_enable,
145 .disable = clk_pxa3xx_cken_disable,
146 };
147
148 const struct clkops clk_pxa3xx_hsio_ops = {
149 .enable = clk_pxa3xx_cken_enable,
150 .disable = clk_pxa3xx_cken_disable,
151 .getrate = clk_pxa3xx_hsio_getrate,
152 };
153
154 const struct clkops clk_pxa3xx_ac97_ops = {
155 .enable = clk_pxa3xx_cken_enable,
156 .disable = clk_pxa3xx_cken_disable,
157 .getrate = clk_pxa3xx_ac97_getrate,
158 };
159
160 const struct clkops clk_pxa3xx_smemc_ops = {
161 .enable = clk_pxa3xx_cken_enable,
162 .disable = clk_pxa3xx_cken_disable,
163 .getrate = clk_pxa3xx_smemc_getrate,
164 };
165
clk_pout_enable(struct clk * clk)166 static void clk_pout_enable(struct clk *clk)
167 {
168 OSCC |= OSCC_PEN;
169 }
170
clk_pout_disable(struct clk * clk)171 static void clk_pout_disable(struct clk *clk)
172 {
173 OSCC &= ~OSCC_PEN;
174 }
175
176 const struct clkops clk_pxa3xx_pout_ops = {
177 .enable = clk_pout_enable,
178 .disable = clk_pout_disable,
179 };
180
181 #ifdef CONFIG_PM
182 static uint32_t cken[2];
183 static uint32_t accr;
184
pxa3xx_clock_suspend(struct sys_device * d,pm_message_t state)185 static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state)
186 {
187 cken[0] = CKENA;
188 cken[1] = CKENB;
189 accr = ACCR;
190 return 0;
191 }
192
pxa3xx_clock_resume(struct sys_device * d)193 static int pxa3xx_clock_resume(struct sys_device *d)
194 {
195 ACCR = accr;
196 CKENA = cken[0];
197 CKENB = cken[1];
198 return 0;
199 }
200 #else
201 #define pxa3xx_clock_suspend NULL
202 #define pxa3xx_clock_resume NULL
203 #endif
204
205 struct sysdev_class pxa3xx_clock_sysclass = {
206 .name = "pxa3xx-clock",
207 .suspend = pxa3xx_clock_suspend,
208 .resume = pxa3xx_clock_resume,
209 };
210
pxa3xx_clock_init(void)211 static int __init pxa3xx_clock_init(void)
212 {
213 if (cpu_is_pxa3xx() || cpu_is_pxa95x())
214 return sysdev_class_register(&pxa3xx_clock_sysclass);
215 return 0;
216 }
217 postcore_initcall(pxa3xx_clock_init);
218