1 /*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21 #include <linux/pm.h>
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <linux/console.h>
32 #include <trace/events/power.h>
33
34 #include <plat/sram.h>
35 #include "clockdomain.h"
36 #include "powerdomain.h"
37 #include <plat/serial.h>
38 #include <plat/sdrc.h>
39 #include <plat/prcm.h>
40 #include <plat/gpmc.h>
41 #include <plat/dma.h>
42
43 #include <asm/tlbflush.h>
44
45 #include "cm2xxx_3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
48
49 #include "prm2xxx_3xxx.h"
50 #include "pm.h"
51 #include "sdrc.h"
52 #include "control.h"
53
54 #ifdef CONFIG_SUSPEND
55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
is_suspending(void)56 static inline bool is_suspending(void)
57 {
58 return (suspend_state != PM_SUSPEND_ON);
59 }
60 #else
is_suspending(void)61 static inline bool is_suspending(void)
62 {
63 return false;
64 }
65 #endif
66
67 /* Scratchpad offsets */
68 #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4
69 #define OMAP343X_TABLE_VALUE_OFFSET 0xc0
70 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
71
72 /* pm34xx errata defined in pm.h */
73 u16 pm34xx_errata;
74
75 struct power_state {
76 struct powerdomain *pwrdm;
77 u32 next_state;
78 #ifdef CONFIG_SUSPEND
79 u32 saved_state;
80 #endif
81 struct list_head node;
82 };
83
84 static LIST_HEAD(pwrst_list);
85
86 static void (*_omap_sram_idle)(u32 *addr, int save_state);
87
88 static int (*_omap_save_secure_sram)(u32 *addr);
89
90 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
91 static struct powerdomain *core_pwrdm, *per_pwrdm;
92 static struct powerdomain *cam_pwrdm;
93
omap3_per_save_context(void)94 static inline void omap3_per_save_context(void)
95 {
96 omap_gpio_save_context();
97 }
98
omap3_per_restore_context(void)99 static inline void omap3_per_restore_context(void)
100 {
101 omap_gpio_restore_context();
102 }
103
omap3_enable_io_chain(void)104 static void omap3_enable_io_chain(void)
105 {
106 int timeout = 0;
107
108 if (omap_rev() >= OMAP3430_REV_ES3_1) {
109 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
110 PM_WKEN);
111 /* Do a readback to assure write has been done */
112 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
113
114 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
115 OMAP3430_ST_IO_CHAIN_MASK)) {
116 timeout++;
117 if (timeout > 1000) {
118 printk(KERN_ERR "Wake up daisy chain "
119 "activation failed.\n");
120 return;
121 }
122 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
123 WKUP_MOD, PM_WKEN);
124 }
125 }
126 }
127
omap3_disable_io_chain(void)128 static void omap3_disable_io_chain(void)
129 {
130 if (omap_rev() >= OMAP3430_REV_ES3_1)
131 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
132 PM_WKEN);
133 }
134
omap3_core_save_context(void)135 static void omap3_core_save_context(void)
136 {
137 omap3_ctrl_save_padconf();
138
139 /*
140 * Force write last pad into memory, as this can fail in some
141 * cases according to errata 1.157, 1.185
142 */
143 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
144 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
145
146 /* Save the Interrupt controller context */
147 omap_intc_save_context();
148 /* Save the GPMC context */
149 omap3_gpmc_save_context();
150 /* Save the system control module context, padconf already save above*/
151 omap3_control_save_context();
152 omap_dma_global_context_save();
153 }
154
omap3_core_restore_context(void)155 static void omap3_core_restore_context(void)
156 {
157 /* Restore the control module context, padconf restored by h/w */
158 omap3_control_restore_context();
159 /* Restore the GPMC context */
160 omap3_gpmc_restore_context();
161 /* Restore the interrupt controller context */
162 omap_intc_restore_context();
163 omap_dma_global_context_restore();
164 }
165
166 /*
167 * FIXME: This function should be called before entering off-mode after
168 * OMAP3 secure services have been accessed. Currently it is only called
169 * once during boot sequence, but this works as we are not using secure
170 * services.
171 */
omap3_save_secure_ram_context(void)172 static void omap3_save_secure_ram_context(void)
173 {
174 u32 ret;
175 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
176
177 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
178 /*
179 * MPU next state must be set to POWER_ON temporarily,
180 * otherwise the WFI executed inside the ROM code
181 * will hang the system.
182 */
183 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
184 ret = _omap_save_secure_sram((u32 *)
185 __pa(omap3_secure_ram_storage));
186 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
187 /* Following is for error tracking, it should not happen */
188 if (ret) {
189 printk(KERN_ERR "save_secure_sram() returns %08x\n",
190 ret);
191 while (1)
192 ;
193 }
194 }
195 }
196
197 /*
198 * PRCM Interrupt Handler Helper Function
199 *
200 * The purpose of this function is to clear any wake-up events latched
201 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
202 * may occur whilst attempting to clear a PM_WKST_x register and thus
203 * set another bit in this register. A while loop is used to ensure
204 * that any peripheral wake-up events occurring while attempting to
205 * clear the PM_WKST_x are detected and cleared.
206 */
prcm_clear_mod_irqs(s16 module,u8 regs)207 static int prcm_clear_mod_irqs(s16 module, u8 regs)
208 {
209 u32 wkst, fclk, iclk, clken;
210 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
211 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
212 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
213 u16 grpsel_off = (regs == 3) ?
214 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
215 int c = 0;
216
217 wkst = omap2_prm_read_mod_reg(module, wkst_off);
218 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
219 if (wkst) {
220 iclk = omap2_cm_read_mod_reg(module, iclk_off);
221 fclk = omap2_cm_read_mod_reg(module, fclk_off);
222 while (wkst) {
223 clken = wkst;
224 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
225 /*
226 * For USBHOST, we don't know whether HOST1 or
227 * HOST2 woke us up, so enable both f-clocks
228 */
229 if (module == OMAP3430ES2_USBHOST_MOD)
230 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
231 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
232 omap2_prm_write_mod_reg(wkst, module, wkst_off);
233 wkst = omap2_prm_read_mod_reg(module, wkst_off);
234 c++;
235 }
236 omap2_cm_write_mod_reg(iclk, module, iclk_off);
237 omap2_cm_write_mod_reg(fclk, module, fclk_off);
238 }
239
240 return c;
241 }
242
_prcm_int_handle_wakeup(void)243 static int _prcm_int_handle_wakeup(void)
244 {
245 int c;
246
247 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
248 c += prcm_clear_mod_irqs(CORE_MOD, 1);
249 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
250 if (omap_rev() > OMAP3430_REV_ES1_0) {
251 c += prcm_clear_mod_irqs(CORE_MOD, 3);
252 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
253 }
254
255 return c;
256 }
257
258 /*
259 * PRCM Interrupt Handler
260 *
261 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
262 * interrupts from the PRCM for the MPU. These bits must be cleared in
263 * order to clear the PRCM interrupt. The PRCM interrupt handler is
264 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
265 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
266 * register indicates that a wake-up event is pending for the MPU and
267 * this bit can only be cleared if the all the wake-up events latched
268 * in the various PM_WKST_x registers have been cleared. The interrupt
269 * handler is implemented using a do-while loop so that if a wake-up
270 * event occurred during the processing of the prcm interrupt handler
271 * (setting a bit in the corresponding PM_WKST_x register and thus
272 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
273 * this would be handled.
274 */
prcm_interrupt_handler(int irq,void * dev_id)275 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
276 {
277 u32 irqenable_mpu, irqstatus_mpu;
278 int c = 0;
279
280 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
281 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
282 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
283 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
284 irqstatus_mpu &= irqenable_mpu;
285
286 do {
287 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
288 OMAP3430_IO_ST_MASK)) {
289 c = _prcm_int_handle_wakeup();
290
291 /*
292 * Is the MPU PRCM interrupt handler racing with the
293 * IVA2 PRCM interrupt handler ?
294 */
295 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
296 "but no wakeup sources are marked\n");
297 } else {
298 /* XXX we need to expand our PRCM interrupt handler */
299 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
300 "no code to handle it (%08x)\n", irqstatus_mpu);
301 }
302
303 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
304 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
305
306 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
307 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
308 irqstatus_mpu &= irqenable_mpu;
309
310 } while (irqstatus_mpu);
311
312 return IRQ_HANDLED;
313 }
314
315 /* Function to restore the table entry that was modified for enabling MMU */
restore_table_entry(void)316 static void restore_table_entry(void)
317 {
318 void __iomem *scratchpad_address;
319 u32 previous_value, control_reg_value;
320 u32 *address;
321
322 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
323
324 /* Get address of entry that was modified */
325 address = (u32 *)__raw_readl(scratchpad_address +
326 OMAP343X_TABLE_ADDRESS_OFFSET);
327 /* Get the previous value which needs to be restored */
328 previous_value = __raw_readl(scratchpad_address +
329 OMAP343X_TABLE_VALUE_OFFSET);
330 address = __va(address);
331 *address = previous_value;
332 flush_tlb_all();
333 control_reg_value = __raw_readl(scratchpad_address
334 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
335 /* This will enable caches and prediction */
336 set_cr(control_reg_value);
337 }
338
omap_sram_idle(void)339 void omap_sram_idle(void)
340 {
341 /* Variable to tell what needs to be saved and restored
342 * in omap_sram_idle*/
343 /* save_state = 0 => Nothing to save and restored */
344 /* save_state = 1 => Only L1 and logic lost */
345 /* save_state = 2 => Only L2 lost */
346 /* save_state = 3 => L1, L2 and logic lost */
347 int save_state = 0;
348 int mpu_next_state = PWRDM_POWER_ON;
349 int per_next_state = PWRDM_POWER_ON;
350 int core_next_state = PWRDM_POWER_ON;
351 int per_going_off;
352 int core_prev_state, per_prev_state;
353 u32 sdrc_pwr = 0;
354
355 if (!_omap_sram_idle)
356 return;
357
358 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
359 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
360 pwrdm_clear_all_prev_pwrst(core_pwrdm);
361 pwrdm_clear_all_prev_pwrst(per_pwrdm);
362
363 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
364 switch (mpu_next_state) {
365 case PWRDM_POWER_ON:
366 case PWRDM_POWER_RET:
367 /* No need to save context */
368 save_state = 0;
369 break;
370 case PWRDM_POWER_OFF:
371 save_state = 3;
372 break;
373 default:
374 /* Invalid state */
375 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
376 return;
377 }
378 pwrdm_pre_transition();
379
380 /* NEON control */
381 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
382 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
383
384 /* Enable IO-PAD and IO-CHAIN wakeups */
385 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
386 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
387 if (omap3_has_io_wakeup() &&
388 (per_next_state < PWRDM_POWER_ON ||
389 core_next_state < PWRDM_POWER_ON)) {
390 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
391 omap3_enable_io_chain();
392 }
393
394 /* Block console output in case it is on one of the OMAP UARTs */
395 if (!is_suspending())
396 if (per_next_state < PWRDM_POWER_ON ||
397 core_next_state < PWRDM_POWER_ON)
398 if (!console_trylock())
399 goto console_still_active;
400
401 /* PER */
402 if (per_next_state < PWRDM_POWER_ON) {
403 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
404 omap_uart_prepare_idle(2);
405 omap_uart_prepare_idle(3);
406 omap2_gpio_prepare_for_idle(per_going_off);
407 if (per_next_state == PWRDM_POWER_OFF)
408 omap3_per_save_context();
409 }
410
411 /* CORE */
412 if (core_next_state < PWRDM_POWER_ON) {
413 omap_uart_prepare_idle(0);
414 omap_uart_prepare_idle(1);
415 if (core_next_state == PWRDM_POWER_OFF) {
416 omap3_core_save_context();
417 omap3_cm_save_context();
418 }
419 }
420
421 omap3_intc_prepare_idle();
422
423 /*
424 * On EMU/HS devices ROM code restores a SRDC value
425 * from scratchpad which has automatic self refresh on timeout
426 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
427 * Hence store/restore the SDRC_POWER register here.
428 */
429 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
430 omap_type() != OMAP2_DEVICE_TYPE_GP &&
431 core_next_state == PWRDM_POWER_OFF)
432 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
433
434 /*
435 * omap3_arm_context is the location where ARM registers
436 * get saved. The restore path then reads from this
437 * location and restores them back.
438 */
439 _omap_sram_idle(omap3_arm_context, save_state);
440 cpu_init();
441
442 /* Restore normal SDRC POWER settings */
443 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
444 omap_type() != OMAP2_DEVICE_TYPE_GP &&
445 core_next_state == PWRDM_POWER_OFF)
446 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
447
448 /* Restore table entry modified during MMU restoration */
449 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
450 restore_table_entry();
451
452 /* CORE */
453 if (core_next_state < PWRDM_POWER_ON) {
454 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
455 if (core_prev_state == PWRDM_POWER_OFF) {
456 omap3_core_restore_context();
457 omap3_cm_restore_context();
458 omap3_sram_restore_context();
459 omap2_sms_restore_context();
460 }
461 omap_uart_resume_idle(0);
462 omap_uart_resume_idle(1);
463 if (core_next_state == PWRDM_POWER_OFF)
464 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
465 OMAP3430_GR_MOD,
466 OMAP3_PRM_VOLTCTRL_OFFSET);
467 }
468 omap3_intc_resume_idle();
469
470 /* PER */
471 if (per_next_state < PWRDM_POWER_ON) {
472 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
473 omap2_gpio_resume_after_idle();
474 if (per_prev_state == PWRDM_POWER_OFF)
475 omap3_per_restore_context();
476 omap_uart_resume_idle(2);
477 omap_uart_resume_idle(3);
478 }
479
480 if (!is_suspending())
481 console_unlock();
482
483 console_still_active:
484 /* Disable IO-PAD and IO-CHAIN wakeup */
485 if (omap3_has_io_wakeup() &&
486 (per_next_state < PWRDM_POWER_ON ||
487 core_next_state < PWRDM_POWER_ON)) {
488 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
489 PM_WKEN);
490 omap3_disable_io_chain();
491 }
492
493 pwrdm_post_transition();
494
495 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
496 }
497
omap3_can_sleep(void)498 int omap3_can_sleep(void)
499 {
500 if (!sleep_while_idle)
501 return 0;
502 if (!omap_uart_can_sleep())
503 return 0;
504 return 1;
505 }
506
omap3_pm_idle(void)507 static void omap3_pm_idle(void)
508 {
509 local_irq_disable();
510 local_fiq_disable();
511
512 if (!omap3_can_sleep())
513 goto out;
514
515 if (omap_irq_pending() || need_resched())
516 goto out;
517
518 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
519 trace_cpu_idle(1, smp_processor_id());
520
521 omap_sram_idle();
522
523 trace_power_end(smp_processor_id());
524 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
525
526 out:
527 local_fiq_enable();
528 local_irq_enable();
529 }
530
531 #ifdef CONFIG_SUSPEND
omap3_pm_suspend(void)532 static int omap3_pm_suspend(void)
533 {
534 struct power_state *pwrst;
535 int state, ret = 0;
536
537 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
538 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
539 wakeup_timer_milliseconds);
540
541 /* Read current next_pwrsts */
542 list_for_each_entry(pwrst, &pwrst_list, node)
543 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
544 /* Set ones wanted by suspend */
545 list_for_each_entry(pwrst, &pwrst_list, node) {
546 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
547 goto restore;
548 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
549 goto restore;
550 }
551
552 omap_uart_prepare_suspend();
553 omap3_intc_suspend();
554
555 omap_sram_idle();
556
557 restore:
558 /* Restore next_pwrsts */
559 list_for_each_entry(pwrst, &pwrst_list, node) {
560 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
561 if (state > pwrst->next_state) {
562 printk(KERN_INFO "Powerdomain (%s) didn't enter "
563 "target state %d\n",
564 pwrst->pwrdm->name, pwrst->next_state);
565 ret = -1;
566 }
567 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
568 }
569 if (ret)
570 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
571 else
572 printk(KERN_INFO "Successfully put all powerdomains "
573 "to target state\n");
574
575 return ret;
576 }
577
omap3_pm_enter(suspend_state_t unused)578 static int omap3_pm_enter(suspend_state_t unused)
579 {
580 int ret = 0;
581
582 switch (suspend_state) {
583 case PM_SUSPEND_STANDBY:
584 case PM_SUSPEND_MEM:
585 ret = omap3_pm_suspend();
586 break;
587 default:
588 ret = -EINVAL;
589 }
590
591 return ret;
592 }
593
594 /* Hooks to enable / disable UART interrupts during suspend */
omap3_pm_begin(suspend_state_t state)595 static int omap3_pm_begin(suspend_state_t state)
596 {
597 disable_hlt();
598 suspend_state = state;
599 omap_uart_enable_irqs(0);
600 return 0;
601 }
602
omap3_pm_end(void)603 static void omap3_pm_end(void)
604 {
605 suspend_state = PM_SUSPEND_ON;
606 omap_uart_enable_irqs(1);
607 enable_hlt();
608 return;
609 }
610
611 static const struct platform_suspend_ops omap_pm_ops = {
612 .begin = omap3_pm_begin,
613 .end = omap3_pm_end,
614 .enter = omap3_pm_enter,
615 .valid = suspend_valid_only_mem,
616 };
617 #endif /* CONFIG_SUSPEND */
618
619
620 /**
621 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
622 * retention
623 *
624 * In cases where IVA2 is activated by bootcode, it may prevent
625 * full-chip retention or off-mode because it is not idle. This
626 * function forces the IVA2 into idle state so it can go
627 * into retention/off and thus allow full-chip retention/off.
628 *
629 **/
omap3_iva_idle(void)630 static void __init omap3_iva_idle(void)
631 {
632 /* ensure IVA2 clock is disabled */
633 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
634
635 /* if no clock activity, nothing else to do */
636 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
637 OMAP3430_CLKACTIVITY_IVA2_MASK))
638 return;
639
640 /* Reset IVA2 */
641 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
642 OMAP3430_RST2_IVA2_MASK |
643 OMAP3430_RST3_IVA2_MASK,
644 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
645
646 /* Enable IVA2 clock */
647 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
648 OMAP3430_IVA2_MOD, CM_FCLKEN);
649
650 /* Set IVA2 boot mode to 'idle' */
651 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
652 OMAP343X_CONTROL_IVA2_BOOTMOD);
653
654 /* Un-reset IVA2 */
655 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
656
657 /* Disable IVA2 clock */
658 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
659
660 /* Reset IVA2 */
661 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
662 OMAP3430_RST2_IVA2_MASK |
663 OMAP3430_RST3_IVA2_MASK,
664 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
665 }
666
omap3_d2d_idle(void)667 static void __init omap3_d2d_idle(void)
668 {
669 u16 mask, padconf;
670
671 /* In a stand alone OMAP3430 where there is not a stacked
672 * modem for the D2D Idle Ack and D2D MStandby must be pulled
673 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
674 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
675 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
676 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
677 padconf |= mask;
678 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
679
680 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
681 padconf |= mask;
682 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
683
684 /* reset modem */
685 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
686 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
687 CORE_MOD, OMAP2_RM_RSTCTRL);
688 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
689 }
690
prcm_setup_regs(void)691 static void __init prcm_setup_regs(void)
692 {
693 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
694 OMAP3630_EN_UART4_MASK : 0;
695 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
696 OMAP3630_GRPSEL_UART4_MASK : 0;
697
698 /* XXX This should be handled by hwmod code or SCM init code */
699 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
700
701 /*
702 * Enable control of expternal oscillator through
703 * sys_clkreq. In the long run clock framework should
704 * take care of this.
705 */
706 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
707 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
708 OMAP3430_GR_MOD,
709 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
710
711 /* setup wakup source */
712 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
713 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
714 WKUP_MOD, PM_WKEN);
715 /* No need to write EN_IO, that is always enabled */
716 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
717 OMAP3430_GRPSEL_GPT1_MASK |
718 OMAP3430_GRPSEL_GPT12_MASK,
719 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
720 /* For some reason IO doesn't generate wakeup event even if
721 * it is selected to mpu wakeup goup */
722 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
723 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
724
725 /* Enable PM_WKEN to support DSS LPR */
726 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
727 OMAP3430_DSS_MOD, PM_WKEN);
728
729 /* Enable wakeups in PER */
730 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
731 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
732 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
733 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
734 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
735 OMAP3430_EN_MCBSP4_MASK,
736 OMAP3430_PER_MOD, PM_WKEN);
737 /* and allow them to wake up MPU */
738 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
739 OMAP3430_GRPSEL_GPIO2_MASK |
740 OMAP3430_GRPSEL_GPIO3_MASK |
741 OMAP3430_GRPSEL_GPIO4_MASK |
742 OMAP3430_GRPSEL_GPIO5_MASK |
743 OMAP3430_GRPSEL_GPIO6_MASK |
744 OMAP3430_GRPSEL_UART3_MASK |
745 OMAP3430_GRPSEL_MCBSP2_MASK |
746 OMAP3430_GRPSEL_MCBSP3_MASK |
747 OMAP3430_GRPSEL_MCBSP4_MASK,
748 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
749
750 /* Don't attach IVA interrupts */
751 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
752 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
753 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
754 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
755
756 /* Clear any pending 'reset' flags */
757 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
758 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
759 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
760 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
761 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
762 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
763 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
764
765 /* Clear any pending PRCM interrupts */
766 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
767
768 omap3_iva_idle();
769 omap3_d2d_idle();
770 }
771
omap3_pm_off_mode_enable(int enable)772 void omap3_pm_off_mode_enable(int enable)
773 {
774 struct power_state *pwrst;
775 u32 state;
776
777 if (enable)
778 state = PWRDM_POWER_OFF;
779 else
780 state = PWRDM_POWER_RET;
781
782 #ifdef CONFIG_CPU_IDLE
783 /*
784 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
785 * enable OFF mode in a stable form for previous revisions, restrict
786 * instead to RET
787 */
788 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
789 omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
790 else
791 omap3_cpuidle_update_states(state, state);
792 #endif
793
794 list_for_each_entry(pwrst, &pwrst_list, node) {
795 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
796 pwrst->pwrdm == core_pwrdm &&
797 state == PWRDM_POWER_OFF) {
798 pwrst->next_state = PWRDM_POWER_RET;
799 pr_warn("%s: Core OFF disabled due to errata i583\n",
800 __func__);
801 } else {
802 pwrst->next_state = state;
803 }
804 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
805 }
806 }
807
omap3_pm_get_suspend_state(struct powerdomain * pwrdm)808 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
809 {
810 struct power_state *pwrst;
811
812 list_for_each_entry(pwrst, &pwrst_list, node) {
813 if (pwrst->pwrdm == pwrdm)
814 return pwrst->next_state;
815 }
816 return -EINVAL;
817 }
818
omap3_pm_set_suspend_state(struct powerdomain * pwrdm,int state)819 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
820 {
821 struct power_state *pwrst;
822
823 list_for_each_entry(pwrst, &pwrst_list, node) {
824 if (pwrst->pwrdm == pwrdm) {
825 pwrst->next_state = state;
826 return 0;
827 }
828 }
829 return -EINVAL;
830 }
831
pwrdms_setup(struct powerdomain * pwrdm,void * unused)832 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
833 {
834 struct power_state *pwrst;
835
836 if (!pwrdm->pwrsts)
837 return 0;
838
839 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
840 if (!pwrst)
841 return -ENOMEM;
842 pwrst->pwrdm = pwrdm;
843 pwrst->next_state = PWRDM_POWER_RET;
844 list_add(&pwrst->node, &pwrst_list);
845
846 if (pwrdm_has_hdwr_sar(pwrdm))
847 pwrdm_enable_hdwr_sar(pwrdm);
848
849 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
850 }
851
852 /*
853 * Enable hw supervised mode for all clockdomains if it's
854 * supported. Initiate sleep transition for other clockdomains, if
855 * they are not used
856 */
clkdms_setup(struct clockdomain * clkdm,void * unused)857 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
858 {
859 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
860 clkdm_allow_idle(clkdm);
861 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
862 atomic_read(&clkdm->usecount) == 0)
863 clkdm_sleep(clkdm);
864 return 0;
865 }
866
omap_push_sram_idle(void)867 void omap_push_sram_idle(void)
868 {
869 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
870 omap34xx_cpu_suspend_sz);
871 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
872 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
873 save_secure_ram_context_sz);
874 }
875
pm_errata_configure(void)876 static void __init pm_errata_configure(void)
877 {
878 if (cpu_is_omap3630()) {
879 pm34xx_errata |= PM_RTA_ERRATUM_i608;
880 /* Enable the l2 cache toggling in sleep logic */
881 enable_omap3630_toggle_l2_on_restore();
882 if (omap_rev() < OMAP3630_REV_ES1_2)
883 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
884 }
885 }
886
omap3_pm_init(void)887 static int __init omap3_pm_init(void)
888 {
889 struct power_state *pwrst, *tmp;
890 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
891 int ret;
892
893 if (!cpu_is_omap34xx())
894 return -ENODEV;
895
896 pm_errata_configure();
897
898 printk(KERN_ERR "Power Management for TI OMAP3.\n");
899
900 /* XXX prcm_setup_regs needs to be before enabling hw
901 * supervised mode for powerdomains */
902 prcm_setup_regs();
903
904 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
905 (irq_handler_t)prcm_interrupt_handler,
906 IRQF_DISABLED, "prcm", NULL);
907 if (ret) {
908 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
909 INT_34XX_PRCM_MPU_IRQ);
910 goto err1;
911 }
912
913 ret = pwrdm_for_each(pwrdms_setup, NULL);
914 if (ret) {
915 printk(KERN_ERR "Failed to setup powerdomains\n");
916 goto err2;
917 }
918
919 (void) clkdm_for_each(clkdms_setup, NULL);
920
921 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
922 if (mpu_pwrdm == NULL) {
923 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
924 goto err2;
925 }
926
927 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
928 per_pwrdm = pwrdm_lookup("per_pwrdm");
929 core_pwrdm = pwrdm_lookup("core_pwrdm");
930 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
931
932 neon_clkdm = clkdm_lookup("neon_clkdm");
933 mpu_clkdm = clkdm_lookup("mpu_clkdm");
934 per_clkdm = clkdm_lookup("per_clkdm");
935 core_clkdm = clkdm_lookup("core_clkdm");
936
937 omap_push_sram_idle();
938 #ifdef CONFIG_SUSPEND
939 suspend_set_ops(&omap_pm_ops);
940 #endif /* CONFIG_SUSPEND */
941
942 pm_idle = omap3_pm_idle;
943 omap3_idle_init();
944
945 /*
946 * RTA is disabled during initialization as per erratum i608
947 * it is safer to disable RTA by the bootloader, but we would like
948 * to be doubly sure here and prevent any mishaps.
949 */
950 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
951 omap3630_ctrl_disable_rta();
952
953 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
954 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
955 omap3_secure_ram_storage =
956 kmalloc(0x803F, GFP_KERNEL);
957 if (!omap3_secure_ram_storage)
958 printk(KERN_ERR "Memory allocation failed when"
959 "allocating for secure sram context\n");
960
961 local_irq_disable();
962 local_fiq_disable();
963
964 omap_dma_global_context_save();
965 omap3_save_secure_ram_context();
966 omap_dma_global_context_restore();
967
968 local_irq_enable();
969 local_fiq_enable();
970 }
971
972 omap3_save_scratchpad_contents();
973 err1:
974 return ret;
975 err2:
976 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
977 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
978 list_del(&pwrst->node);
979 kfree(pwrst);
980 }
981 return ret;
982 }
983
984 late_initcall(omap3_pm_init);
985