1 /*
2 * CPU idle for DaVinci SoCs
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
5 *
6 * Derived from Marvell Kirkwood CPU idle code
7 * (arch/arm/mach-kirkwood/cpuidle.c)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/cpuidle.h>
18 #include <linux/io.h>
19 #include <asm/proc-fns.h>
20
21 #include <mach/cpuidle.h>
22 #include <mach/memory.h>
23
24 #define DAVINCI_CPUIDLE_MAX_STATES 2
25
26 struct davinci_ops {
27 void (*enter) (u32 flags);
28 void (*exit) (u32 flags);
29 u32 flags;
30 };
31
32 /* fields in davinci_ops.flags */
33 #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
34
35 static struct cpuidle_driver davinci_idle_driver = {
36 .name = "cpuidle-davinci",
37 .owner = THIS_MODULE,
38 };
39
40 static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
41 static void __iomem *ddr2_reg_base;
42
davinci_save_ddr_power(int enter,bool pdown)43 static void davinci_save_ddr_power(int enter, bool pdown)
44 {
45 u32 val;
46
47 val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
48
49 if (enter) {
50 if (pdown)
51 val |= DDR2_SRPD_BIT;
52 else
53 val &= ~DDR2_SRPD_BIT;
54 val |= DDR2_LPMODEN_BIT;
55 } else {
56 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
57 }
58
59 __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
60 }
61
davinci_c2state_enter(u32 flags)62 static void davinci_c2state_enter(u32 flags)
63 {
64 davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
65 }
66
davinci_c2state_exit(u32 flags)67 static void davinci_c2state_exit(u32 flags)
68 {
69 davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
70 }
71
72 static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
73 [1] = {
74 .enter = davinci_c2state_enter,
75 .exit = davinci_c2state_exit,
76 },
77 };
78
79 /* Actual code that puts the SoC in different idle states */
davinci_enter_idle(struct cpuidle_device * dev,struct cpuidle_state * state)80 static int davinci_enter_idle(struct cpuidle_device *dev,
81 struct cpuidle_state *state)
82 {
83 struct davinci_ops *ops = cpuidle_get_statedata(state);
84 struct timeval before, after;
85 int idle_time;
86
87 local_irq_disable();
88 do_gettimeofday(&before);
89
90 if (ops && ops->enter)
91 ops->enter(ops->flags);
92 /* Wait for interrupt state */
93 cpu_do_idle();
94 if (ops && ops->exit)
95 ops->exit(ops->flags);
96
97 do_gettimeofday(&after);
98 local_irq_enable();
99 idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
100 (after.tv_usec - before.tv_usec);
101 return idle_time;
102 }
103
davinci_cpuidle_probe(struct platform_device * pdev)104 static int __init davinci_cpuidle_probe(struct platform_device *pdev)
105 {
106 int ret;
107 struct cpuidle_device *device;
108 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
109
110 device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
111
112 if (!pdata) {
113 dev_err(&pdev->dev, "cannot get platform data\n");
114 return -ENOENT;
115 }
116
117 ddr2_reg_base = pdata->ddr2_ctlr_base;
118
119 ret = cpuidle_register_driver(&davinci_idle_driver);
120 if (ret) {
121 dev_err(&pdev->dev, "failed to register driver\n");
122 return ret;
123 }
124
125 /* Wait for interrupt state */
126 device->states[0].enter = davinci_enter_idle;
127 device->states[0].exit_latency = 1;
128 device->states[0].target_residency = 10000;
129 device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
130 strcpy(device->states[0].name, "WFI");
131 strcpy(device->states[0].desc, "Wait for interrupt");
132
133 /* Wait for interrupt and DDR self refresh state */
134 device->states[1].enter = davinci_enter_idle;
135 device->states[1].exit_latency = 10;
136 device->states[1].target_residency = 10000;
137 device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
138 strcpy(device->states[1].name, "DDR SR");
139 strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
140 if (pdata->ddr2_pdown)
141 davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
142 cpuidle_set_statedata(&device->states[1], &davinci_states[1]);
143
144 device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
145
146 ret = cpuidle_register_device(device);
147 if (ret) {
148 dev_err(&pdev->dev, "failed to register device\n");
149 cpuidle_unregister_driver(&davinci_idle_driver);
150 return ret;
151 }
152
153 return 0;
154 }
155
156 static struct platform_driver davinci_cpuidle_driver = {
157 .driver = {
158 .name = "cpuidle-davinci",
159 .owner = THIS_MODULE,
160 },
161 };
162
davinci_cpuidle_init(void)163 static int __init davinci_cpuidle_init(void)
164 {
165 return platform_driver_probe(&davinci_cpuidle_driver,
166 davinci_cpuidle_probe);
167 }
168 device_initcall(davinci_cpuidle_init);
169
170