1 #ifdef CONFIG_ARCH_AT91RM9200
2 #include <mach/at91rm9200_mc.h>
3
4 /*
5 * The AT91RM9200 goes into self-refresh mode with this command, and will
6 * terminate self-refresh automatically on the next SDRAM access.
7 *
8 * Self-refresh mode is exited as soon as a memory access is made, but we don't
9 * know for sure when that happens. However, we need to restore the low-power
10 * mode if it was enabled before going idle. Restoring low-power mode while
11 * still in self-refresh is "not recommended", but seems to work.
12 */
13
sdram_selfrefresh_enable(void)14 static inline u32 sdram_selfrefresh_enable(void)
15 {
16 u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
17
18 at91_sys_write(AT91_SDRAMC_LPR, 0);
19 at91_sys_write(AT91_SDRAMC_SRR, 1);
20 return saved_lpr;
21 }
22
23 #define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
24 #define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
25 : : "r" (0))
26
27 #elif defined(CONFIG_ARCH_AT91CAP9)
28 #include <mach/at91cap9_ddrsdr.h>
29
30
sdram_selfrefresh_enable(void)31 static inline u32 sdram_selfrefresh_enable(void)
32 {
33 u32 saved_lpr, lpr;
34
35 saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
36
37 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
38 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
39 return saved_lpr;
40 }
41
42 #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
43 #define wait_for_interrupt_enable() cpu_do_idle()
44
45 #elif defined(CONFIG_ARCH_AT91SAM9G45)
46 #include <mach/at91sam9_ddrsdr.h>
47
48 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
49 * remember.
50 */
51 static u32 saved_lpr1;
52
sdram_selfrefresh_enable(void)53 static inline u32 sdram_selfrefresh_enable(void)
54 {
55 /* Those tow values allow us to delay self-refresh activation
56 * to the maximum. */
57 u32 lpr0, lpr1;
58 u32 saved_lpr0;
59
60 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
61 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
62 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
63
64 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
65 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
66 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
67
68 /* self-refresh mode now */
69 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
70 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
71
72 return saved_lpr0;
73 }
74
75 #define sdram_selfrefresh_disable(saved_lpr0) \
76 do { \
77 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
78 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
79 } while (0)
80 #define wait_for_interrupt_enable() cpu_do_idle()
81
82 #else
83 #include <mach/at91sam9_sdramc.h>
84
85 #ifdef CONFIG_ARCH_AT91SAM9263
86 /*
87 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
88 * handle those cases both here and in the Suspend-To-RAM support.
89 */
90 #warning Assuming EB1 SDRAM controller is *NOT* used
91 #endif
92
sdram_selfrefresh_enable(void)93 static inline u32 sdram_selfrefresh_enable(void)
94 {
95 u32 saved_lpr, lpr;
96
97 saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
98
99 lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
100 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
101 return saved_lpr;
102 }
103
104 #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
105 #define wait_for_interrupt_enable() cpu_do_idle()
106
107 #endif
108