1 /*
2 * linux/arch/alpha/kernel/sys_dp264.c
3 *
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996, 1999 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 *
8 * Modified by Christopher C. Chimelis, 2001 to
9 * add support for the addition of Shark to the
10 * Tsunami family.
11 *
12 * Code supporting the DP264 (EV6+TSUNAMI).
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/mm.h>
18 #include <linux/sched.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/bitops.h>
22
23 #include <asm/ptrace.h>
24 #include <asm/system.h>
25 #include <asm/dma.h>
26 #include <asm/irq.h>
27 #include <asm/mmu_context.h>
28 #include <asm/io.h>
29 #include <asm/pgtable.h>
30 #include <asm/core_tsunami.h>
31 #include <asm/hwrpb.h>
32 #include <asm/tlbflush.h>
33
34 #include "proto.h"
35 #include "irq_impl.h"
36 #include "pci_impl.h"
37 #include "machvec_impl.h"
38
39
40 /* Note mask bit is true for ENABLED irqs. */
41 static unsigned long cached_irq_mask;
42 /* dp264 boards handle at max four CPUs */
43 static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };
44
45 DEFINE_SPINLOCK(dp264_irq_lock);
46
47 static void
tsunami_update_irq_hw(unsigned long mask)48 tsunami_update_irq_hw(unsigned long mask)
49 {
50 register tsunami_cchip *cchip = TSUNAMI_cchip;
51 unsigned long isa_enable = 1UL << 55;
52 register int bcpu = boot_cpuid;
53
54 #ifdef CONFIG_SMP
55 volatile unsigned long *dim0, *dim1, *dim2, *dim3;
56 unsigned long mask0, mask1, mask2, mask3, dummy;
57
58 mask &= ~isa_enable;
59 mask0 = mask & cpu_irq_affinity[0];
60 mask1 = mask & cpu_irq_affinity[1];
61 mask2 = mask & cpu_irq_affinity[2];
62 mask3 = mask & cpu_irq_affinity[3];
63
64 if (bcpu == 0) mask0 |= isa_enable;
65 else if (bcpu == 1) mask1 |= isa_enable;
66 else if (bcpu == 2) mask2 |= isa_enable;
67 else mask3 |= isa_enable;
68
69 dim0 = &cchip->dim0.csr;
70 dim1 = &cchip->dim1.csr;
71 dim2 = &cchip->dim2.csr;
72 dim3 = &cchip->dim3.csr;
73 if (!cpu_possible(0)) dim0 = &dummy;
74 if (!cpu_possible(1)) dim1 = &dummy;
75 if (!cpu_possible(2)) dim2 = &dummy;
76 if (!cpu_possible(3)) dim3 = &dummy;
77
78 *dim0 = mask0;
79 *dim1 = mask1;
80 *dim2 = mask2;
81 *dim3 = mask3;
82 mb();
83 *dim0;
84 *dim1;
85 *dim2;
86 *dim3;
87 #else
88 volatile unsigned long *dimB;
89 if (bcpu == 0) dimB = &cchip->dim0.csr;
90 else if (bcpu == 1) dimB = &cchip->dim1.csr;
91 else if (bcpu == 2) dimB = &cchip->dim2.csr;
92 else dimB = &cchip->dim3.csr;
93
94 *dimB = mask | isa_enable;
95 mb();
96 *dimB;
97 #endif
98 }
99
100 static void
dp264_enable_irq(struct irq_data * d)101 dp264_enable_irq(struct irq_data *d)
102 {
103 spin_lock(&dp264_irq_lock);
104 cached_irq_mask |= 1UL << d->irq;
105 tsunami_update_irq_hw(cached_irq_mask);
106 spin_unlock(&dp264_irq_lock);
107 }
108
109 static void
dp264_disable_irq(struct irq_data * d)110 dp264_disable_irq(struct irq_data *d)
111 {
112 spin_lock(&dp264_irq_lock);
113 cached_irq_mask &= ~(1UL << d->irq);
114 tsunami_update_irq_hw(cached_irq_mask);
115 spin_unlock(&dp264_irq_lock);
116 }
117
118 static void
clipper_enable_irq(struct irq_data * d)119 clipper_enable_irq(struct irq_data *d)
120 {
121 spin_lock(&dp264_irq_lock);
122 cached_irq_mask |= 1UL << (d->irq - 16);
123 tsunami_update_irq_hw(cached_irq_mask);
124 spin_unlock(&dp264_irq_lock);
125 }
126
127 static void
clipper_disable_irq(struct irq_data * d)128 clipper_disable_irq(struct irq_data *d)
129 {
130 spin_lock(&dp264_irq_lock);
131 cached_irq_mask &= ~(1UL << (d->irq - 16));
132 tsunami_update_irq_hw(cached_irq_mask);
133 spin_unlock(&dp264_irq_lock);
134 }
135
136 static void
cpu_set_irq_affinity(unsigned int irq,cpumask_t affinity)137 cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
138 {
139 int cpu;
140
141 for (cpu = 0; cpu < 4; cpu++) {
142 unsigned long aff = cpu_irq_affinity[cpu];
143 if (cpu_isset(cpu, affinity))
144 aff |= 1UL << irq;
145 else
146 aff &= ~(1UL << irq);
147 cpu_irq_affinity[cpu] = aff;
148 }
149 }
150
151 static int
dp264_set_affinity(struct irq_data * d,const struct cpumask * affinity,bool force)152 dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
153 bool force)
154 {
155 spin_lock(&dp264_irq_lock);
156 cpu_set_irq_affinity(d->irq, *affinity);
157 tsunami_update_irq_hw(cached_irq_mask);
158 spin_unlock(&dp264_irq_lock);
159
160 return 0;
161 }
162
163 static int
clipper_set_affinity(struct irq_data * d,const struct cpumask * affinity,bool force)164 clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
165 bool force)
166 {
167 spin_lock(&dp264_irq_lock);
168 cpu_set_irq_affinity(d->irq - 16, *affinity);
169 tsunami_update_irq_hw(cached_irq_mask);
170 spin_unlock(&dp264_irq_lock);
171
172 return 0;
173 }
174
175 static struct irq_chip dp264_irq_type = {
176 .name = "DP264",
177 .irq_unmask = dp264_enable_irq,
178 .irq_mask = dp264_disable_irq,
179 .irq_mask_ack = dp264_disable_irq,
180 .irq_set_affinity = dp264_set_affinity,
181 };
182
183 static struct irq_chip clipper_irq_type = {
184 .name = "CLIPPER",
185 .irq_unmask = clipper_enable_irq,
186 .irq_mask = clipper_disable_irq,
187 .irq_mask_ack = clipper_disable_irq,
188 .irq_set_affinity = clipper_set_affinity,
189 };
190
191 static void
dp264_device_interrupt(unsigned long vector)192 dp264_device_interrupt(unsigned long vector)
193 {
194 #if 1
195 printk("dp264_device_interrupt: NOT IMPLEMENTED YET!!\n");
196 #else
197 unsigned long pld;
198 unsigned int i;
199
200 /* Read the interrupt summary register of TSUNAMI */
201 pld = TSUNAMI_cchip->dir0.csr;
202
203 /*
204 * Now for every possible bit set, work through them and call
205 * the appropriate interrupt handler.
206 */
207 while (pld) {
208 i = ffz(~pld);
209 pld &= pld - 1; /* clear least bit set */
210 if (i == 55)
211 isa_device_interrupt(vector);
212 else
213 handle_irq(16 + i);
214 #if 0
215 TSUNAMI_cchip->dir0.csr = 1UL << i; mb();
216 tmp = TSUNAMI_cchip->dir0.csr;
217 #endif
218 }
219 #endif
220 }
221
222 static void
dp264_srm_device_interrupt(unsigned long vector)223 dp264_srm_device_interrupt(unsigned long vector)
224 {
225 int irq;
226
227 irq = (vector - 0x800) >> 4;
228
229 /*
230 * The SRM console reports PCI interrupts with a vector calculated by:
231 *
232 * 0x900 + (0x10 * DRIR-bit)
233 *
234 * So bit 16 shows up as IRQ 32, etc.
235 *
236 * On DP264/BRICK/MONET, we adjust it down by 16 because at least
237 * that many of the low order bits of the DRIR are not used, and
238 * so we don't count them.
239 */
240 if (irq >= 32)
241 irq -= 16;
242
243 handle_irq(irq);
244 }
245
246 static void
clipper_srm_device_interrupt(unsigned long vector)247 clipper_srm_device_interrupt(unsigned long vector)
248 {
249 int irq;
250
251 irq = (vector - 0x800) >> 4;
252
253 /*
254 * The SRM console reports PCI interrupts with a vector calculated by:
255 *
256 * 0x900 + (0x10 * DRIR-bit)
257 *
258 * So bit 16 shows up as IRQ 32, etc.
259 *
260 * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
261 * to scale down the vector reported, we just use it.
262 *
263 * Eg IRQ 24 is DRIR bit 8, etc, etc
264 */
265 handle_irq(irq);
266 }
267
268 static void __init
init_tsunami_irqs(struct irq_chip * ops,int imin,int imax)269 init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
270 {
271 long i;
272 for (i = imin; i <= imax; ++i) {
273 irq_set_chip_and_handler(i, ops, handle_level_irq);
274 irq_set_status_flags(i, IRQ_LEVEL);
275 }
276 }
277
278 static void __init
dp264_init_irq(void)279 dp264_init_irq(void)
280 {
281 outb(0, DMA1_RESET_REG);
282 outb(0, DMA2_RESET_REG);
283 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
284 outb(0, DMA2_MASK_REG);
285
286 if (alpha_using_srm)
287 alpha_mv.device_interrupt = dp264_srm_device_interrupt;
288
289 tsunami_update_irq_hw(0);
290
291 init_i8259a_irqs();
292 init_tsunami_irqs(&dp264_irq_type, 16, 47);
293 }
294
295 static void __init
clipper_init_irq(void)296 clipper_init_irq(void)
297 {
298 outb(0, DMA1_RESET_REG);
299 outb(0, DMA2_RESET_REG);
300 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
301 outb(0, DMA2_MASK_REG);
302
303 if (alpha_using_srm)
304 alpha_mv.device_interrupt = clipper_srm_device_interrupt;
305
306 tsunami_update_irq_hw(0);
307
308 init_i8259a_irqs();
309 init_tsunami_irqs(&clipper_irq_type, 24, 63);
310 }
311
312
313 /*
314 * PCI Fixup configuration.
315 *
316 * Summary @ TSUNAMI_CSR_DIM0:
317 * Bit Meaning
318 * 0-17 Unused
319 *18 Interrupt SCSI B (Adaptec 7895 builtin)
320 *19 Interrupt SCSI A (Adaptec 7895 builtin)
321 *20 Interrupt Line D from slot 2 PCI0
322 *21 Interrupt Line C from slot 2 PCI0
323 *22 Interrupt Line B from slot 2 PCI0
324 *23 Interrupt Line A from slot 2 PCI0
325 *24 Interrupt Line D from slot 1 PCI0
326 *25 Interrupt Line C from slot 1 PCI0
327 *26 Interrupt Line B from slot 1 PCI0
328 *27 Interrupt Line A from slot 1 PCI0
329 *28 Interrupt Line D from slot 0 PCI0
330 *29 Interrupt Line C from slot 0 PCI0
331 *30 Interrupt Line B from slot 0 PCI0
332 *31 Interrupt Line A from slot 0 PCI0
333 *
334 *32 Interrupt Line D from slot 3 PCI1
335 *33 Interrupt Line C from slot 3 PCI1
336 *34 Interrupt Line B from slot 3 PCI1
337 *35 Interrupt Line A from slot 3 PCI1
338 *36 Interrupt Line D from slot 2 PCI1
339 *37 Interrupt Line C from slot 2 PCI1
340 *38 Interrupt Line B from slot 2 PCI1
341 *39 Interrupt Line A from slot 2 PCI1
342 *40 Interrupt Line D from slot 1 PCI1
343 *41 Interrupt Line C from slot 1 PCI1
344 *42 Interrupt Line B from slot 1 PCI1
345 *43 Interrupt Line A from slot 1 PCI1
346 *44 Interrupt Line D from slot 0 PCI1
347 *45 Interrupt Line C from slot 0 PCI1
348 *46 Interrupt Line B from slot 0 PCI1
349 *47 Interrupt Line A from slot 0 PCI1
350 *48-52 Unused
351 *53 PCI0 NMI (from Cypress)
352 *54 PCI0 SMI INT (from Cypress)
353 *55 PCI0 ISA Interrupt (from Cypress)
354 *56-60 Unused
355 *61 PCI1 Bus Error
356 *62 PCI0 Bus Error
357 *63 Reserved
358 *
359 * IdSel
360 * 5 Cypress Bridge I/O
361 * 6 SCSI Adaptec builtin
362 * 7 64 bit PCI option slot 0 (all busses)
363 * 8 64 bit PCI option slot 1 (all busses)
364 * 9 64 bit PCI option slot 2 (all busses)
365 * 10 64 bit PCI option slot 3 (not bus 0)
366 */
367
368 static int __init
isa_irq_fixup(struct pci_dev * dev,int irq)369 isa_irq_fixup(struct pci_dev *dev, int irq)
370 {
371 u8 irq8;
372
373 if (irq > 0)
374 return irq;
375
376 /* This interrupt is routed via ISA bridge, so we'll
377 just have to trust whatever value the console might
378 have assigned. */
379 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
380
381 return irq8 & 0xf;
382 }
383
384 static int __init
dp264_map_irq(struct pci_dev * dev,u8 slot,u8 pin)385 dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
386 {
387 static char irq_tab[6][5] __initdata = {
388 /*INT INTA INTB INTC INTD */
389 { -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */
390 { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
391 { 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
392 { 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
393 { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
394 { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
395 };
396 const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
397 struct pci_controller *hose = dev->sysdata;
398 int irq = COMMON_TABLE_LOOKUP;
399
400 if (irq > 0)
401 irq += 16 * hose->index;
402
403 return isa_irq_fixup(dev, irq);
404 }
405
406 static int __init
monet_map_irq(struct pci_dev * dev,u8 slot,u8 pin)407 monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
408 {
409 static char irq_tab[13][5] __initdata = {
410 /*INT INTA INTB INTC INTD */
411 { 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */
412 { -1, -1, -1, -1, -1}, /* IdSel 4 unused */
413 { -1, -1, -1, -1, -1}, /* IdSel 5 unused */
414 { 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */
415 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
416 { -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */
417 #if 1
418 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
419 { 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/
420 #else
421 { -1, -1, -1, -1, -1}, /* IdSel 9 unused */
422 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
423 #endif
424 { 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/
425 { 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/
426 { 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/
427 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
428 { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
429 };
430 const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
431
432 return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
433 }
434
435 static u8 __init
monet_swizzle(struct pci_dev * dev,u8 * pinp)436 monet_swizzle(struct pci_dev *dev, u8 *pinp)
437 {
438 struct pci_controller *hose = dev->sysdata;
439 int slot, pin = *pinp;
440
441 if (!dev->bus->parent) {
442 slot = PCI_SLOT(dev->devfn);
443 }
444 /* Check for the built-in bridge on hose 1. */
445 else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
446 slot = PCI_SLOT(dev->devfn);
447 } else {
448 /* Must be a card-based bridge. */
449 do {
450 /* Check for built-in bridge on hose 1. */
451 if (hose->index == 1 &&
452 PCI_SLOT(dev->bus->self->devfn) == 8) {
453 slot = PCI_SLOT(dev->devfn);
454 break;
455 }
456 pin = pci_swizzle_interrupt_pin(dev, pin);
457
458 /* Move up the chain of bridges. */
459 dev = dev->bus->self;
460 /* Slot of the next bridge. */
461 slot = PCI_SLOT(dev->devfn);
462 } while (dev->bus->self);
463 }
464 *pinp = pin;
465 return slot;
466 }
467
468 static int __init
webbrick_map_irq(struct pci_dev * dev,u8 slot,u8 pin)469 webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
470 {
471 static char irq_tab[13][5] __initdata = {
472 /*INT INTA INTB INTC INTD */
473 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
474 { -1, -1, -1, -1, -1}, /* IdSel 8 unused */
475 { 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */
476 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
477 { 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */
478 { -1, -1, -1, -1, -1}, /* IdSel 12 unused */
479 { -1, -1, -1, -1, -1}, /* IdSel 13 unused */
480 { 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */
481 { 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */
482 { 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */
483 { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
484 };
485 const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
486
487 return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP);
488 }
489
490 static int __init
clipper_map_irq(struct pci_dev * dev,u8 slot,u8 pin)491 clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
492 {
493 static char irq_tab[7][5] __initdata = {
494 /*INT INTA INTB INTC INTD */
495 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
496 { 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
497 { 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
498 { 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
499 { 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
500 { 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
501 { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
502 };
503 const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
504 struct pci_controller *hose = dev->sysdata;
505 int irq = COMMON_TABLE_LOOKUP;
506
507 if (irq > 0)
508 irq += 16 * hose->index;
509
510 return isa_irq_fixup(dev, irq);
511 }
512
513 static void __init
dp264_init_pci(void)514 dp264_init_pci(void)
515 {
516 common_init_pci();
517 SMC669_Init(0);
518 locate_and_init_vga(NULL);
519 }
520
521 static void __init
monet_init_pci(void)522 monet_init_pci(void)
523 {
524 common_init_pci();
525 SMC669_Init(1);
526 es1888_init();
527 locate_and_init_vga(NULL);
528 }
529
530 static void __init
clipper_init_pci(void)531 clipper_init_pci(void)
532 {
533 common_init_pci();
534 locate_and_init_vga(NULL);
535 }
536
537 static void __init
webbrick_init_arch(void)538 webbrick_init_arch(void)
539 {
540 tsunami_init_arch();
541
542 /* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */
543 hose_head->sg_isa->align_entry = 4;
544 hose_head->sg_pci->align_entry = 4;
545 }
546
547
548 /*
549 * The System Vectors
550 */
551
552 struct alpha_machine_vector dp264_mv __initmv = {
553 .vector_name = "DP264",
554 DO_EV6_MMU,
555 DO_DEFAULT_RTC,
556 DO_TSUNAMI_IO,
557 .machine_check = tsunami_machine_check,
558 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
559 .min_io_address = DEFAULT_IO_BASE,
560 .min_mem_address = DEFAULT_MEM_BASE,
561 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
562
563 .nr_irqs = 64,
564 .device_interrupt = dp264_device_interrupt,
565
566 .init_arch = tsunami_init_arch,
567 .init_irq = dp264_init_irq,
568 .init_rtc = common_init_rtc,
569 .init_pci = dp264_init_pci,
570 .kill_arch = tsunami_kill_arch,
571 .pci_map_irq = dp264_map_irq,
572 .pci_swizzle = common_swizzle,
573 };
574 ALIAS_MV(dp264)
575
576 struct alpha_machine_vector monet_mv __initmv = {
577 .vector_name = "Monet",
578 DO_EV6_MMU,
579 DO_DEFAULT_RTC,
580 DO_TSUNAMI_IO,
581 .machine_check = tsunami_machine_check,
582 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
583 .min_io_address = DEFAULT_IO_BASE,
584 .min_mem_address = DEFAULT_MEM_BASE,
585 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
586
587 .nr_irqs = 64,
588 .device_interrupt = dp264_device_interrupt,
589
590 .init_arch = tsunami_init_arch,
591 .init_irq = dp264_init_irq,
592 .init_rtc = common_init_rtc,
593 .init_pci = monet_init_pci,
594 .kill_arch = tsunami_kill_arch,
595 .pci_map_irq = monet_map_irq,
596 .pci_swizzle = monet_swizzle,
597 };
598
599 struct alpha_machine_vector webbrick_mv __initmv = {
600 .vector_name = "Webbrick",
601 DO_EV6_MMU,
602 DO_DEFAULT_RTC,
603 DO_TSUNAMI_IO,
604 .machine_check = tsunami_machine_check,
605 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
606 .min_io_address = DEFAULT_IO_BASE,
607 .min_mem_address = DEFAULT_MEM_BASE,
608 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
609
610 .nr_irqs = 64,
611 .device_interrupt = dp264_device_interrupt,
612
613 .init_arch = webbrick_init_arch,
614 .init_irq = dp264_init_irq,
615 .init_rtc = common_init_rtc,
616 .init_pci = common_init_pci,
617 .kill_arch = tsunami_kill_arch,
618 .pci_map_irq = webbrick_map_irq,
619 .pci_swizzle = common_swizzle,
620 };
621
622 struct alpha_machine_vector clipper_mv __initmv = {
623 .vector_name = "Clipper",
624 DO_EV6_MMU,
625 DO_DEFAULT_RTC,
626 DO_TSUNAMI_IO,
627 .machine_check = tsunami_machine_check,
628 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
629 .min_io_address = DEFAULT_IO_BASE,
630 .min_mem_address = DEFAULT_MEM_BASE,
631 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
632
633 .nr_irqs = 64,
634 .device_interrupt = dp264_device_interrupt,
635
636 .init_arch = tsunami_init_arch,
637 .init_irq = clipper_init_irq,
638 .init_rtc = common_init_rtc,
639 .init_pci = clipper_init_pci,
640 .kill_arch = tsunami_kill_arch,
641 .pci_map_irq = clipper_map_irq,
642 .pci_swizzle = common_swizzle,
643 };
644
645 /* Sharks strongly resemble Clipper, at least as far
646 * as interrupt routing, etc, so we're using the
647 * same functions as Clipper does
648 */
649
650 struct alpha_machine_vector shark_mv __initmv = {
651 .vector_name = "Shark",
652 DO_EV6_MMU,
653 DO_DEFAULT_RTC,
654 DO_TSUNAMI_IO,
655 .machine_check = tsunami_machine_check,
656 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
657 .min_io_address = DEFAULT_IO_BASE,
658 .min_mem_address = DEFAULT_MEM_BASE,
659 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
660
661 .nr_irqs = 64,
662 .device_interrupt = dp264_device_interrupt,
663
664 .init_arch = tsunami_init_arch,
665 .init_irq = clipper_init_irq,
666 .init_rtc = common_init_rtc,
667 .init_pci = common_init_pci,
668 .kill_arch = tsunami_kill_arch,
669 .pci_map_irq = clipper_map_irq,
670 .pci_swizzle = common_swizzle,
671 };
672
673 /* No alpha_mv alias for webbrick/monet/clipper, since we compile them
674 in unconditionally with DP264; setup_arch knows how to cope. */
675