1 STMicroelectronics 10/100/1000 Synopsys Ethernet driver 2 3Copyright (C) 2007-2010 STMicroelectronics Ltd 4Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 5 6This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers 7(Synopsys IP blocks); it has been fully tested on STLinux platforms. 8 9Currently this network device driver is for all STM embedded MAC/GMAC 10(7xxx SoCs). Other platforms start using it i.e. ARM SPEAr. 11 12DWC Ether MAC 10/100/1000 Universal version 3.41a and DWC Ether MAC 10/100 13Universal version 4.0 have been used for developing the first code 14implementation. 15 16Please, for more information also visit: www.stlinux.com 17 181) Kernel Configuration 19The kernel configuration option is STMMAC_ETH: 20 Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) ---> 21 STMicroelectronics 10/100/1000 Ethernet driver (STMMAC_ETH) 22 232) Driver parameters list: 24 debug: message level (0: no output, 16: all); 25 phyaddr: to manually provide the physical address to the PHY device; 26 dma_rxsize: DMA rx ring size; 27 dma_txsize: DMA tx ring size; 28 buf_sz: DMA buffer size; 29 tc: control the HW FIFO threshold; 30 tx_coe: Enable/Disable Tx Checksum Offload engine; 31 watchdog: transmit timeout (in milliseconds); 32 flow_ctrl: Flow control ability [on/off]; 33 pause: Flow Control Pause Time; 34 tmrate: timer period (only if timer optimisation is configured). 35 363) Command line options 37Driver parameters can be also passed in command line by using: 38 stmmaceth=dma_rxsize:128,dma_txsize:512 39 404) Driver information and notes 41 424.1) Transmit process 43The xmit method is invoked when the kernel needs to transmit a packet; it sets 44the descriptors in the ring and informs the DMA engine that there is a packet 45ready to be transmitted. 46Once the controller has finished transmitting the packet, an interrupt is 47triggered; So the driver will be able to release the socket buffers. 48By default, the driver sets the NETIF_F_SG bit in the features field of the 49net_device structure enabling the scatter/gather feature. 50 514.2) Receive process 52When one or more packets are received, an interrupt happens. The interrupts 53are not queued so the driver has to scan all the descriptors in the ring during 54the receive process. 55This is based on NAPI so the interrupt handler signals only if there is work to be 56done, and it exits. 57Then the poll method will be scheduled at some future point. 58The incoming packets are stored, by the DMA, in a list of pre-allocated socket 59buffers in order to avoid the memcpy (Zero-copy). 60 614.3) Timer-Driver Interrupt 62Instead of having the device that asynchronously notifies the frame receptions, the 63driver configures a timer to generate an interrupt at regular intervals. 64Based on the granularity of the timer, the frames that are received by the device 65will experience different levels of latency. Some NICs have dedicated timer 66device to perform this task. STMMAC can use either the RTC device or the TMU 67channel 2 on STLinux platforms. 68The timers frequency can be passed to the driver as parameter; when change it, 69take care of both hardware capability and network stability/performance impact. 70Several performance tests on STM platforms showed this optimisation allows to spare 71the CPU while having the maximum throughput. 72 734.4) WOL 74Wake up on Lan feature through Magic Frame is only supported for the GMAC 75core. 76 774.5) DMA descriptors 78Driver handles both normal and enhanced descriptors. The latter has been only 79tested on DWC Ether MAC 10/100/1000 Universal version 3.41a. 80 814.6) Ethtool support 82Ethtool is supported. Driver statistics and internal errors can be taken using: 83ethtool -S ethX command. It is possible to dump registers etc. 84 854.7) Jumbo and Segmentation Offloading 86Jumbo frames are supported and tested for the GMAC. 87The GSO has been also added but it's performed in software. 88LRO is not supported. 89 904.8) Physical 91The driver is compatible with PAL to work with PHY and GPHY devices. 92 934.9) Platform information 94Several information came from the platform; please refer to the 95driver's Header file in include/linux directory. 96 97struct plat_stmmacenet_data { 98 int bus_id; 99 int pbl; 100 int clk_csr; 101 int has_gmac; 102 int enh_desc; 103 int tx_coe; 104 int bugged_jumbo; 105 int pmt; 106 void (*fix_mac_speed)(void *priv, unsigned int speed); 107 void (*bus_setup)(unsigned long ioaddr); 108#ifdef CONFIG_STM_DRIVERS 109 struct stm_pad_config *pad_config; 110#endif 111 void *bsp_priv; 112}; 113 114Where: 115- pbl (Programmable Burst Length) is maximum number of 116 beats to be transferred in one DMA transaction. 117 GMAC also enables the 4xPBL by default. 118- fix_mac_speed and bus_setup are used to configure internal target 119 registers (on STM platforms); 120- has_gmac: GMAC core is on board (get it at run-time in the next step); 121- bus_id: bus identifier. 122- tx_coe: core is able to perform the tx csum in HW. 123- enh_desc: if sets the MAC will use the enhanced descriptor structure. 124- clk_csr: CSR Clock range selection. 125- bugged_jumbo: some HWs are not able to perform the csum in HW for 126 over-sized frames due to limited buffer sizes. Setting this 127 flag the csum will be done in SW on JUMBO frames. 128 129struct plat_stmmacphy_data { 130 int bus_id; 131 int phy_addr; 132 unsigned int phy_mask; 133 int interface; 134 int (*phy_reset)(void *priv); 135 void *priv; 136}; 137 138Where: 139- bus_id: bus identifier; 140- phy_addr: physical address used for the attached phy device; 141 set it to -1 to get it at run-time; 142- interface: physical MII interface mode; 143- phy_reset: hook to reset HW function. 144 145SOURCES: 146- Kconfig 147- Makefile 148- stmmac_main.c: main network device driver; 149- stmmac_mdio.c: mdio functions; 150- stmmac_ethtool.c: ethtool support; 151- stmmac_timer.[ch]: timer code used for mitigating the driver dma interrupts 152 Only tested on ST40 platforms based. 153- stmmac.h: private driver structure; 154- common.h: common definitions and VFTs; 155- descs.h: descriptor structure definitions; 156- dwmac1000_core.c: GMAC core functions; 157- dwmac1000_dma.c: dma functions for the GMAC chip; 158- dwmac1000.h: specific header file for the GMAC; 159- dwmac100_core: MAC 100 core and dma code; 160- dwmac100_dma.c: dma funtions for the MAC chip; 161- dwmac1000.h: specific header file for the MAC; 162- dwmac_lib.c: generic DMA functions shared among chips 163- enh_desc.c: functions for handling enhanced descriptors 164- norm_desc.c: functions for handling normal descriptors 165 166TODO: 167- XGMAC controller is not supported. 168- Review the timer optimisation code to use an embedded device that seems to be 169 available in new chip generations. 170