1<?xml version="1.0" encoding="UTF-8"?> 2<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN" 3 "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []> 4 5<book id="Generic-IRQ-Guide"> 6 <bookinfo> 7 <title>Linux generic IRQ handling</title> 8 9 <authorgroup> 10 <author> 11 <firstname>Thomas</firstname> 12 <surname>Gleixner</surname> 13 <affiliation> 14 <address> 15 <email>tglx@linutronix.de</email> 16 </address> 17 </affiliation> 18 </author> 19 <author> 20 <firstname>Ingo</firstname> 21 <surname>Molnar</surname> 22 <affiliation> 23 <address> 24 <email>mingo@elte.hu</email> 25 </address> 26 </affiliation> 27 </author> 28 </authorgroup> 29 30 <copyright> 31 <year>2005-2010</year> 32 <holder>Thomas Gleixner</holder> 33 </copyright> 34 <copyright> 35 <year>2005-2006</year> 36 <holder>Ingo Molnar</holder> 37 </copyright> 38 39 <legalnotice> 40 <para> 41 This documentation is free software; you can redistribute 42 it and/or modify it under the terms of the GNU General Public 43 License version 2 as published by the Free Software Foundation. 44 </para> 45 46 <para> 47 This program is distributed in the hope that it will be 48 useful, but WITHOUT ANY WARRANTY; without even the implied 49 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 50 See the GNU General Public License for more details. 51 </para> 52 53 <para> 54 You should have received a copy of the GNU General Public 55 License along with this program; if not, write to the Free 56 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, 57 MA 02111-1307 USA 58 </para> 59 60 <para> 61 For more details see the file COPYING in the source 62 distribution of Linux. 63 </para> 64 </legalnotice> 65 </bookinfo> 66 67<toc></toc> 68 69 <chapter id="intro"> 70 <title>Introduction</title> 71 <para> 72 The generic interrupt handling layer is designed to provide a 73 complete abstraction of interrupt handling for device drivers. 74 It is able to handle all the different types of interrupt controller 75 hardware. Device drivers use generic API functions to request, enable, 76 disable and free interrupts. The drivers do not have to know anything 77 about interrupt hardware details, so they can be used on different 78 platforms without code changes. 79 </para> 80 <para> 81 This documentation is provided to developers who want to implement 82 an interrupt subsystem based for their architecture, with the help 83 of the generic IRQ handling layer. 84 </para> 85 </chapter> 86 87 <chapter id="rationale"> 88 <title>Rationale</title> 89 <para> 90 The original implementation of interrupt handling in Linux is using 91 the __do_IRQ() super-handler, which is able to deal with every 92 type of interrupt logic. 93 </para> 94 <para> 95 Originally, Russell King identified different types of handlers to 96 build a quite universal set for the ARM interrupt handler 97 implementation in Linux 2.5/2.6. He distinguished between: 98 <itemizedlist> 99 <listitem><para>Level type</para></listitem> 100 <listitem><para>Edge type</para></listitem> 101 <listitem><para>Simple type</para></listitem> 102 </itemizedlist> 103 During the implementation we identified another type: 104 <itemizedlist> 105 <listitem><para>Fast EOI type</para></listitem> 106 </itemizedlist> 107 In the SMP world of the __do_IRQ() super-handler another type 108 was identified: 109 <itemizedlist> 110 <listitem><para>Per CPU type</para></listitem> 111 </itemizedlist> 112 </para> 113 <para> 114 This split implementation of highlevel IRQ handlers allows us to 115 optimize the flow of the interrupt handling for each specific 116 interrupt type. This reduces complexity in that particular codepath 117 and allows the optimized handling of a given type. 118 </para> 119 <para> 120 The original general IRQ implementation used hw_interrupt_type 121 structures and their ->ack(), ->end() [etc.] callbacks to 122 differentiate the flow control in the super-handler. This leads to 123 a mix of flow logic and lowlevel hardware logic, and it also leads 124 to unnecessary code duplication: for example in i386, there is a 125 ioapic_level_irq and a ioapic_edge_irq irq-type which share many 126 of the lowlevel details but have different flow handling. 127 </para> 128 <para> 129 A more natural abstraction is the clean separation of the 130 'irq flow' and the 'chip details'. 131 </para> 132 <para> 133 Analysing a couple of architecture's IRQ subsystem implementations 134 reveals that most of them can use a generic set of 'irq flow' 135 methods and only need to add the chip level specific code. 136 The separation is also valuable for (sub)architectures 137 which need specific quirks in the irq flow itself but not in the 138 chip-details - and thus provides a more transparent IRQ subsystem 139 design. 140 </para> 141 <para> 142 Each interrupt descriptor is assigned its own highlevel flow 143 handler, which is normally one of the generic 144 implementations. (This highlevel flow handler implementation also 145 makes it simple to provide demultiplexing handlers which can be 146 found in embedded platforms on various architectures.) 147 </para> 148 <para> 149 The separation makes the generic interrupt handling layer more 150 flexible and extensible. For example, an (sub)architecture can 151 use a generic irq-flow implementation for 'level type' interrupts 152 and add a (sub)architecture specific 'edge type' implementation. 153 </para> 154 <para> 155 To make the transition to the new model easier and prevent the 156 breakage of existing implementations, the __do_IRQ() super-handler 157 is still available. This leads to a kind of duality for the time 158 being. Over time the new model should be used in more and more 159 architectures, as it enables smaller and cleaner IRQ subsystems. 160 It's deprecated for three years now and about to be removed. 161 </para> 162 </chapter> 163 <chapter id="bugs"> 164 <title>Known Bugs And Assumptions</title> 165 <para> 166 None (knock on wood). 167 </para> 168 </chapter> 169 170 <chapter id="Abstraction"> 171 <title>Abstraction layers</title> 172 <para> 173 There are three main levels of abstraction in the interrupt code: 174 <orderedlist> 175 <listitem><para>Highlevel driver API</para></listitem> 176 <listitem><para>Highlevel IRQ flow handlers</para></listitem> 177 <listitem><para>Chiplevel hardware encapsulation</para></listitem> 178 </orderedlist> 179 </para> 180 <sect1 id="Interrupt_control_flow"> 181 <title>Interrupt control flow</title> 182 <para> 183 Each interrupt is described by an interrupt descriptor structure 184 irq_desc. The interrupt is referenced by an 'unsigned int' numeric 185 value which selects the corresponding interrupt decription structure 186 in the descriptor structures array. 187 The descriptor structure contains status information and pointers 188 to the interrupt flow method and the interrupt chip structure 189 which are assigned to this interrupt. 190 </para> 191 <para> 192 Whenever an interrupt triggers, the lowlevel arch code calls into 193 the generic interrupt code by calling desc->handle_irq(). 194 This highlevel IRQ handling function only uses desc->chip primitives 195 referenced by the assigned chip descriptor structure. 196 </para> 197 </sect1> 198 <sect1 id="Highlevel_Driver_API"> 199 <title>Highlevel Driver API</title> 200 <para> 201 The highlevel Driver API consists of following functions: 202 <itemizedlist> 203 <listitem><para>request_irq()</para></listitem> 204 <listitem><para>free_irq()</para></listitem> 205 <listitem><para>disable_irq()</para></listitem> 206 <listitem><para>enable_irq()</para></listitem> 207 <listitem><para>disable_irq_nosync() (SMP only)</para></listitem> 208 <listitem><para>synchronize_irq() (SMP only)</para></listitem> 209 <listitem><para>set_irq_type()</para></listitem> 210 <listitem><para>set_irq_wake()</para></listitem> 211 <listitem><para>set_irq_data()</para></listitem> 212 <listitem><para>set_irq_chip()</para></listitem> 213 <listitem><para>set_irq_chip_data()</para></listitem> 214 </itemizedlist> 215 See the autogenerated function documentation for details. 216 </para> 217 </sect1> 218 <sect1 id="Highlevel_IRQ_flow_handlers"> 219 <title>Highlevel IRQ flow handlers</title> 220 <para> 221 The generic layer provides a set of pre-defined irq-flow methods: 222 <itemizedlist> 223 <listitem><para>handle_level_irq</para></listitem> 224 <listitem><para>handle_edge_irq</para></listitem> 225 <listitem><para>handle_fasteoi_irq</para></listitem> 226 <listitem><para>handle_simple_irq</para></listitem> 227 <listitem><para>handle_percpu_irq</para></listitem> 228 </itemizedlist> 229 The interrupt flow handlers (either predefined or architecture 230 specific) are assigned to specific interrupts by the architecture 231 either during bootup or during device initialization. 232 </para> 233 <sect2 id="Default_flow_implementations"> 234 <title>Default flow implementations</title> 235 <sect3 id="Helper_functions"> 236 <title>Helper functions</title> 237 <para> 238 The helper functions call the chip primitives and 239 are used by the default flow implementations. 240 The following helper functions are implemented (simplified excerpt): 241 <programlisting> 242default_enable(struct irq_data *data) 243{ 244 desc->chip->irq_unmask(data); 245} 246 247default_disable(struct irq_data *data) 248{ 249 if (!delay_disable(data)) 250 desc->chip->irq_mask(data); 251} 252 253default_ack(struct irq_data *data) 254{ 255 chip->irq_ack(data); 256} 257 258default_mask_ack(struct irq_data *data) 259{ 260 if (chip->irq_mask_ack) { 261 chip->irq_mask_ack(data); 262 } else { 263 chip->irq_mask(data); 264 chip->irq_ack(data); 265 } 266} 267 268noop(struct irq_data *data)) 269{ 270} 271 272 </programlisting> 273 </para> 274 </sect3> 275 </sect2> 276 <sect2 id="Default_flow_handler_implementations"> 277 <title>Default flow handler implementations</title> 278 <sect3 id="Default_Level_IRQ_flow_handler"> 279 <title>Default Level IRQ flow handler</title> 280 <para> 281 handle_level_irq provides a generic implementation 282 for level-triggered interrupts. 283 </para> 284 <para> 285 The following control flow is implemented (simplified excerpt): 286 <programlisting> 287desc->chip->irq_mask(); 288handle_IRQ_event(desc->action); 289desc->chip->irq_unmask(); 290 </programlisting> 291 </para> 292 </sect3> 293 <sect3 id="Default_FASTEOI_IRQ_flow_handler"> 294 <title>Default Fast EOI IRQ flow handler</title> 295 <para> 296 handle_fasteoi_irq provides a generic implementation 297 for interrupts, which only need an EOI at the end of 298 the handler 299 </para> 300 <para> 301 The following control flow is implemented (simplified excerpt): 302 <programlisting> 303handle_IRQ_event(desc->action); 304desc->chip->irq_eoi(); 305 </programlisting> 306 </para> 307 </sect3> 308 <sect3 id="Default_Edge_IRQ_flow_handler"> 309 <title>Default Edge IRQ flow handler</title> 310 <para> 311 handle_edge_irq provides a generic implementation 312 for edge-triggered interrupts. 313 </para> 314 <para> 315 The following control flow is implemented (simplified excerpt): 316 <programlisting> 317if (desc->status & running) { 318 desc->chip->irq_mask(); 319 desc->status |= pending | masked; 320 return; 321} 322desc->chip->irq_ack(); 323desc->status |= running; 324do { 325 if (desc->status & masked) 326 desc->chip->irq_unmask(); 327 desc->status &= ~pending; 328 handle_IRQ_event(desc->action); 329} while (status & pending); 330desc->status &= ~running; 331 </programlisting> 332 </para> 333 </sect3> 334 <sect3 id="Default_simple_IRQ_flow_handler"> 335 <title>Default simple IRQ flow handler</title> 336 <para> 337 handle_simple_irq provides a generic implementation 338 for simple interrupts. 339 </para> 340 <para> 341 Note: The simple flow handler does not call any 342 handler/chip primitives. 343 </para> 344 <para> 345 The following control flow is implemented (simplified excerpt): 346 <programlisting> 347handle_IRQ_event(desc->action); 348 </programlisting> 349 </para> 350 </sect3> 351 <sect3 id="Default_per_CPU_flow_handler"> 352 <title>Default per CPU flow handler</title> 353 <para> 354 handle_percpu_irq provides a generic implementation 355 for per CPU interrupts. 356 </para> 357 <para> 358 Per CPU interrupts are only available on SMP and 359 the handler provides a simplified version without 360 locking. 361 </para> 362 <para> 363 The following control flow is implemented (simplified excerpt): 364 <programlisting> 365handle_IRQ_event(desc->action); 366if (desc->chip->irq_eoi) 367 desc->chip->irq_eoi(); 368 </programlisting> 369 </para> 370 </sect3> 371 </sect2> 372 <sect2 id="Quirks_and_optimizations"> 373 <title>Quirks and optimizations</title> 374 <para> 375 The generic functions are intended for 'clean' architectures and chips, 376 which have no platform-specific IRQ handling quirks. If an architecture 377 needs to implement quirks on the 'flow' level then it can do so by 378 overriding the highlevel irq-flow handler. 379 </para> 380 </sect2> 381 <sect2 id="Delayed_interrupt_disable"> 382 <title>Delayed interrupt disable</title> 383 <para> 384 This per interrupt selectable feature, which was introduced by Russell 385 King in the ARM interrupt implementation, does not mask an interrupt 386 at the hardware level when disable_irq() is called. The interrupt is 387 kept enabled and is masked in the flow handler when an interrupt event 388 happens. This prevents losing edge interrupts on hardware which does 389 not store an edge interrupt event while the interrupt is disabled at 390 the hardware level. When an interrupt arrives while the IRQ_DISABLED 391 flag is set, then the interrupt is masked at the hardware level and 392 the IRQ_PENDING bit is set. When the interrupt is re-enabled by 393 enable_irq() the pending bit is checked and if it is set, the 394 interrupt is resent either via hardware or by a software resend 395 mechanism. (It's necessary to enable CONFIG_HARDIRQS_SW_RESEND when 396 you want to use the delayed interrupt disable feature and your 397 hardware is not capable of retriggering an interrupt.) 398 The delayed interrupt disable is not configurable. 399 </para> 400 </sect2> 401 </sect1> 402 <sect1 id="Chiplevel_hardware_encapsulation"> 403 <title>Chiplevel hardware encapsulation</title> 404 <para> 405 The chip level hardware descriptor structure irq_chip 406 contains all the direct chip relevant functions, which 407 can be utilized by the irq flow implementations. 408 <itemizedlist> 409 <listitem><para>irq_ack()</para></listitem> 410 <listitem><para>irq_mask_ack() - Optional, recommended for performance</para></listitem> 411 <listitem><para>irq_mask()</para></listitem> 412 <listitem><para>irq_unmask()</para></listitem> 413 <listitem><para>irq_retrigger() - Optional</para></listitem> 414 <listitem><para>irq_set_type() - Optional</para></listitem> 415 <listitem><para>irq_set_wake() - Optional</para></listitem> 416 </itemizedlist> 417 These primitives are strictly intended to mean what they say: ack means 418 ACK, masking means masking of an IRQ line, etc. It is up to the flow 419 handler(s) to use these basic units of lowlevel functionality. 420 </para> 421 </sect1> 422 </chapter> 423 424 <chapter id="doirq"> 425 <title>__do_IRQ entry point</title> 426 <para> 427 The original implementation __do_IRQ() is an alternative entry 428 point for all types of interrupts. 429 </para> 430 <para> 431 This handler turned out to be not suitable for all 432 interrupt hardware and was therefore reimplemented with split 433 functionality for egde/level/simple/percpu interrupts. This is not 434 only a functional optimization. It also shortens code paths for 435 interrupts. 436 </para> 437 <para> 438 To make use of the split implementation, replace the call to 439 __do_IRQ by a call to desc->handle_irq() and associate 440 the appropriate handler function to desc->handle_irq(). 441 In most cases the generic handler implementations should 442 be sufficient. 443 </para> 444 </chapter> 445 446 <chapter id="locking"> 447 <title>Locking on SMP</title> 448 <para> 449 The locking of chip registers is up to the architecture that 450 defines the chip primitives. There is a chip->lock field that can be used 451 for serialization, but the generic layer does not touch it. The per-irq 452 structure is protected via desc->lock, by the generic layer. 453 </para> 454 </chapter> 455 <chapter id="structs"> 456 <title>Structures</title> 457 <para> 458 This chapter contains the autogenerated documentation of the structures which are 459 used in the generic IRQ layer. 460 </para> 461!Iinclude/linux/irq.h 462!Iinclude/linux/interrupt.h 463 </chapter> 464 465 <chapter id="pubfunctions"> 466 <title>Public Functions Provided</title> 467 <para> 468 This chapter contains the autogenerated documentation of the kernel API functions 469 which are exported. 470 </para> 471!Ekernel/irq/manage.c 472!Ekernel/irq/chip.c 473 </chapter> 474 475 <chapter id="intfunctions"> 476 <title>Internal Functions Provided</title> 477 <para> 478 This chapter contains the autogenerated documentation of the internal functions. 479 </para> 480!Ikernel/irq/irqdesc.c 481!Ikernel/irq/handle.c 482!Ikernel/irq/chip.c 483 </chapter> 484 485 <chapter id="credits"> 486 <title>Credits</title> 487 <para> 488 The following people have contributed to this document: 489 <orderedlist> 490 <listitem><para>Thomas Gleixner<email>tglx@linutronix.de</email></para></listitem> 491 <listitem><para>Ingo Molnar<email>mingo@elte.hu</email></para></listitem> 492 </orderedlist> 493 </para> 494 </chapter> 495</book> 496