1 /*
2 * I2O kernel space accessible structures/APIs
3 *
4 * (c) Copyright 1999, 2000 Red Hat Software
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 *************************************************************************
12 *
13 * This header file defined the I2O APIs/structures for use by
14 * the I2O kernel modules.
15 *
16 */
17
18 #ifndef _I2O_H
19 #define _I2O_H
20
21 #ifdef __KERNEL__ /* This file to be included by kernel only */
22
23 #include <linux/i2o-dev.h>
24
25 /* How many different OSM's are we allowing */
26 #define MAX_I2O_MODULES 64
27
28 /* How many OSMs can register themselves for device status updates? */
29 #define I2O_MAX_MANAGERS 4
30
31 #include <asm/semaphore.h> /* Needed for MUTEX init macros */
32 #include <linux/config.h>
33 #include <linux/notifier.h>
34 #include <asm/atomic.h>
35
36 /*
37 * Message structures
38 */
39 struct i2o_message
40 {
41 u8 version_offset;
42 u8 flags;
43 u16 size;
44 u32 target_tid:12;
45 u32 init_tid:12;
46 u32 function:8;
47 u32 initiator_context;
48 /* List follows */
49 };
50
51 /*
52 * Each I2O device entity has one or more of these. There is one
53 * per device.
54 */
55 struct i2o_device
56 {
57 i2o_lct_entry lct_data; /* Device LCT information */
58 u32 flags;
59 int i2oversion; /* I2O version supported. Actually
60 * there should be high and low
61 * version */
62
63 struct proc_dir_entry *proc_entry; /* /proc dir */
64
65 /* Primary user */
66 struct i2o_handler *owner;
67
68 /* Management users */
69 struct i2o_handler *managers[I2O_MAX_MANAGERS];
70 int num_managers;
71
72 struct i2o_controller *controller; /* Controlling IOP */
73 struct i2o_device *next; /* Chain */
74 struct i2o_device *prev;
75 char dev_name[8]; /* linux /dev name if available */
76 };
77
78 /*
79 * Resource data for each PCI I2O controller
80 */
81 struct i2o_pci
82 {
83 int irq;
84 int short_req:1; /* Use small block sizes */
85 int dpt:1; /* Don't quiesce */
86 int promise:1; /* Promise controller */
87 #ifdef CONFIG_MTRR
88 int mtrr_reg0;
89 int mtrr_reg1;
90 #endif
91 };
92
93 /*
94 * Transport types supported by I2O stack
95 */
96 #define I2O_TYPE_PCI 0x01 /* PCI I2O controller */
97
98
99 /*
100 * Each I2O controller has one of these objects
101 */
102 struct i2o_controller
103 {
104 struct pci_dev *pdev; /* PCI device */
105
106 char name[16];
107 int unit;
108 int type;
109 int enabled;
110
111 struct notifier_block *event_notifer; /* Events */
112 atomic_t users;
113 struct i2o_device *devices; /* I2O device chain */
114 struct i2o_controller *next; /* Controller chain */
115 unsigned long post_port; /* Inbout port address */
116 unsigned long reply_port; /* Outbound port address */
117 unsigned long irq_mask; /* Interrupt register address */
118
119 /* Dynamic LCT related data */
120 struct semaphore lct_sem;
121 int lct_pid;
122 int lct_running;
123
124 i2o_status_block *status_block; /* IOP status block */
125 i2o_lct *lct; /* Logical Config Table */
126 i2o_lct *dlct; /* Temp LCT */
127 i2o_hrt *hrt; /* HW Resource Table */
128
129 unsigned long mem_offset; /* MFA offset */
130 unsigned long mem_phys; /* MFA physical */
131
132 int battery:1; /* Has a battery backup */
133 int io_alloc:1; /* An I/O resource was allocated */
134 int mem_alloc:1; /* A memory resource was allocated */
135
136 struct resource io_resource; /* I/O resource allocated to the IOP */
137 struct resource mem_resource; /* Mem resource allocated to the IOP */
138
139 struct proc_dir_entry *proc_entry; /* /proc dir */
140
141 union { /* Bus information */
142 struct i2o_pci pci;
143 } bus;
144
145 /* Bus specific destructor */
146 void (*destructor)(struct i2o_controller *);
147
148 /* Bus specific attach/detach */
149 int (*bind)(struct i2o_controller *, struct i2o_device *);
150
151 /* Bus specific initiator */
152 int (*unbind)(struct i2o_controller *, struct i2o_device *);
153
154 /* Bus specific enable/disable */
155 void (*bus_enable)(struct i2o_controller *);
156 void (*bus_disable)(struct i2o_controller *);
157
158 void *page_frame; /* Message buffers */
159 dma_addr_t page_frame_map; /* Cache map */
160 };
161
162 /*
163 * OSM resgistration block
164 *
165 * Each OSM creates at least one of these and registers it with the
166 * I2O core through i2o_register_handler. An OSM may want to
167 * register more than one if it wants a fast path to a reply
168 * handler by having a separate initiator context for each
169 * class function.
170 */
171 struct i2o_handler
172 {
173 /* Message reply handler */
174 void (*reply)(struct i2o_handler *, struct i2o_controller *,
175 struct i2o_message *);
176
177 /* New device notification handler */
178 void (*new_dev_notify)(struct i2o_controller *, struct i2o_device *);
179
180 /* Device deltion handler */
181 void (*dev_del_notify)(struct i2o_controller *, struct i2o_device *);
182
183 /* Reboot notification handler */
184 void (*reboot_notify)(void);
185
186 char *name; /* OSM name */
187 int context; /* Low 8 bits of the transaction info */
188 u32 class; /* I2O classes that this driver handles */
189 /* User data follows */
190 };
191
192 #ifdef MODULE
193 /*
194 * Used by bus specific modules to communicate with the core
195 *
196 * This is needed because the bus modules cannot make direct
197 * calls to the core as this results in the i2o_bus_specific_module
198 * being dependent on the core, not the otherway around.
199 * In that case, a 'modprobe i2o_lan' loads i2o_core & i2o_lan,
200 * but _not_ i2o_pci...which makes the whole thing pretty useless :)
201 *
202 */
203 struct i2o_core_func_table
204 {
205 int (*install)(struct i2o_controller *);
206 int (*activate)(struct i2o_controller *);
207 struct i2o_controller *(*find)(int);
208 void (*unlock)(struct i2o_controller *);
209 void (*run_queue)(struct i2o_controller * c);
210 int (*delete)(struct i2o_controller *);
211 };
212 #endif /* MODULE */
213
214 /*
215 * I2O System table entry
216 *
217 * The system table contains information about all the IOPs in the
218 * system. It is sent to all IOPs so that they can create peer2peer
219 * connections between them.
220 */
221 struct i2o_sys_tbl_entry
222 {
223 u16 org_id;
224 u16 reserved1;
225 u32 iop_id:12;
226 u32 reserved2:20;
227 u16 seg_num:12;
228 u16 i2o_version:4;
229 u8 iop_state;
230 u8 msg_type;
231 u16 frame_size;
232 u16 reserved3;
233 u32 last_changed;
234 u32 iop_capabilities;
235 u32 inbound_low;
236 u32 inbound_high;
237 };
238
239 struct i2o_sys_tbl
240 {
241 u8 num_entries;
242 u8 version;
243 u16 reserved1;
244 u32 change_ind;
245 u32 reserved2;
246 u32 reserved3;
247 struct i2o_sys_tbl_entry iops[0];
248 };
249
250 /*
251 * Messenger inlines
252 */
I2O_POST_READ32(struct i2o_controller * c)253 static inline u32 I2O_POST_READ32(struct i2o_controller *c)
254 {
255 return readl(c->post_port);
256 }
257
I2O_POST_WRITE32(struct i2o_controller * c,u32 val)258 static inline void I2O_POST_WRITE32(struct i2o_controller *c, u32 val)
259 {
260 writel(val, c->post_port);
261 }
262
263
I2O_REPLY_READ32(struct i2o_controller * c)264 static inline u32 I2O_REPLY_READ32(struct i2o_controller *c)
265 {
266 return readl(c->reply_port);
267 }
268
I2O_REPLY_WRITE32(struct i2o_controller * c,u32 val)269 static inline void I2O_REPLY_WRITE32(struct i2o_controller *c, u32 val)
270 {
271 writel(val, c->reply_port);
272 }
273
274
I2O_IRQ_READ32(struct i2o_controller * c)275 static inline u32 I2O_IRQ_READ32(struct i2o_controller *c)
276 {
277 return readl(c->irq_mask);
278 }
279
I2O_IRQ_WRITE32(struct i2o_controller * c,u32 val)280 static inline void I2O_IRQ_WRITE32(struct i2o_controller *c, u32 val)
281 {
282 writel(val, c->irq_mask);
283 }
284
285
i2o_post_message(struct i2o_controller * c,u32 m)286 static inline void i2o_post_message(struct i2o_controller *c, u32 m)
287 {
288 /* The second line isnt spurious - thats forcing PCI posting */
289 I2O_POST_WRITE32(c, m);
290 (void) I2O_IRQ_READ32(c);
291 }
292
i2o_flush_reply(struct i2o_controller * c,u32 m)293 static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
294 {
295 I2O_REPLY_WRITE32(c, m);
296 }
297
298 /*
299 * Endian handling wrapped into the macro - keeps the core code
300 * cleaner.
301 */
302
303 #define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem)
304
305 extern struct i2o_controller *i2o_find_controller(int);
306 extern void i2o_unlock_controller(struct i2o_controller *);
307 extern struct i2o_controller *i2o_controller_chain;
308 extern int i2o_num_controllers;
309 extern int i2o_status_get(struct i2o_controller *);
310
311 extern int i2o_install_handler(struct i2o_handler *);
312 extern int i2o_remove_handler(struct i2o_handler *);
313
314 extern int i2o_claim_device(struct i2o_device *, struct i2o_handler *);
315 extern int i2o_release_device(struct i2o_device *, struct i2o_handler *);
316 extern int i2o_device_notify_on(struct i2o_device *, struct i2o_handler *);
317 extern int i2o_device_notify_off(struct i2o_device *,
318 struct i2o_handler *);
319
320 extern int i2o_post_this(struct i2o_controller *, u32 *, int);
321 extern int i2o_post_wait(struct i2o_controller *, u32 *, int, int);
322 extern int i2o_post_wait_mem(struct i2o_controller *, u32 *, int, int,
323 void *, void *);
324
325 extern int i2o_query_scalar(struct i2o_controller *, int, int, int, void *,
326 int);
327 extern int i2o_set_scalar(struct i2o_controller *, int, int, int, void *,
328 int);
329 extern int i2o_query_table(int, struct i2o_controller *, int, int, int,
330 void *, int, void *, int);
331 extern int i2o_clear_table(struct i2o_controller *, int, int);
332 extern int i2o_row_add_table(struct i2o_controller *, int, int, int,
333 void *, int);
334 extern int i2o_issue_params(int, struct i2o_controller *, int, void *, int,
335 void *, int);
336
337 extern int i2o_event_register(struct i2o_controller *, u32, u32, u32, u32);
338 extern int i2o_event_ack(struct i2o_controller *, u32 *);
339
340 extern void i2o_report_status(const char *, const char *, u32 *);
341 extern void i2o_dump_message(u32 *);
342 extern const char *i2o_get_class_name(int);
343
344 extern int i2o_install_controller(struct i2o_controller *);
345 extern int i2o_activate_controller(struct i2o_controller *);
346 extern void i2o_run_queue(struct i2o_controller *);
347 extern int i2o_delete_controller(struct i2o_controller *);
348
349 /*
350 * Cache strategies
351 */
352
353
354 /* The NULL strategy leaves everything up to the controller. This tends to be a
355 * pessimal but functional choice.
356 */
357 #define CACHE_NULL 0
358 /* Prefetch data when reading. We continually attempt to load the next 32 sectors
359 * into the controller cache.
360 */
361 #define CACHE_PREFETCH 1
362 /* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
363 * into the controller cache. When an I/O is less <= 8K we assume its probably
364 * not sequential and don't prefetch (default)
365 */
366 #define CACHE_SMARTFETCH 2
367 /* Data is written to the cache and then out on to the disk. The I/O must be
368 * physically on the medium before the write is acknowledged (default without
369 * NVRAM)
370 */
371 #define CACHE_WRITETHROUGH 17
372 /* Data is written to the cache and then out on to the disk. The controller
373 * is permitted to write back the cache any way it wants. (default if battery
374 * backed NVRAM is present). It can be useful to set this for swap regardless of
375 * battery state.
376 */
377 #define CACHE_WRITEBACK 18
378 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
379 * write large I/O's directly to disk bypassing the cache to avoid the extra
380 * memory copy hits. Small writes are writeback cached
381 */
382 #define CACHE_SMARTBACK 19
383 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
384 * write large I/O's directly to disk bypassing the cache to avoid the extra
385 * memory copy hits. Small writes are writethrough cached. Suitable for devices
386 * lacking battery backup
387 */
388 #define CACHE_SMARTTHROUGH 20
389
390 /*
391 * Ioctl structures
392 */
393
394
395 #define BLKI2OGRSTRAT _IOR('2', 1, int)
396 #define BLKI2OGWSTRAT _IOR('2', 2, int)
397 #define BLKI2OSRSTRAT _IOW('2', 3, int)
398 #define BLKI2OSWSTRAT _IOW('2', 4, int)
399
400
401
402
403 /*
404 * I2O Function codes
405 */
406
407 /*
408 * Executive Class
409 */
410 #define I2O_CMD_ADAPTER_ASSIGN 0xB3
411 #define I2O_CMD_ADAPTER_READ 0xB2
412 #define I2O_CMD_ADAPTER_RELEASE 0xB5
413 #define I2O_CMD_BIOS_INFO_SET 0xA5
414 #define I2O_CMD_BOOT_DEVICE_SET 0xA7
415 #define I2O_CMD_CONFIG_VALIDATE 0xBB
416 #define I2O_CMD_CONN_SETUP 0xCA
417 #define I2O_CMD_DDM_DESTROY 0xB1
418 #define I2O_CMD_DDM_ENABLE 0xD5
419 #define I2O_CMD_DDM_QUIESCE 0xC7
420 #define I2O_CMD_DDM_RESET 0xD9
421 #define I2O_CMD_DDM_SUSPEND 0xAF
422 #define I2O_CMD_DEVICE_ASSIGN 0xB7
423 #define I2O_CMD_DEVICE_RELEASE 0xB9
424 #define I2O_CMD_HRT_GET 0xA8
425 #define I2O_CMD_ADAPTER_CLEAR 0xBE
426 #define I2O_CMD_ADAPTER_CONNECT 0xC9
427 #define I2O_CMD_ADAPTER_RESET 0xBD
428 #define I2O_CMD_LCT_NOTIFY 0xA2
429 #define I2O_CMD_OUTBOUND_INIT 0xA1
430 #define I2O_CMD_PATH_ENABLE 0xD3
431 #define I2O_CMD_PATH_QUIESCE 0xC5
432 #define I2O_CMD_PATH_RESET 0xD7
433 #define I2O_CMD_STATIC_MF_CREATE 0xDD
434 #define I2O_CMD_STATIC_MF_RELEASE 0xDF
435 #define I2O_CMD_STATUS_GET 0xA0
436 #define I2O_CMD_SW_DOWNLOAD 0xA9
437 #define I2O_CMD_SW_UPLOAD 0xAB
438 #define I2O_CMD_SW_REMOVE 0xAD
439 #define I2O_CMD_SYS_ENABLE 0xD1
440 #define I2O_CMD_SYS_MODIFY 0xC1
441 #define I2O_CMD_SYS_QUIESCE 0xC3
442 #define I2O_CMD_SYS_TAB_SET 0xA3
443
444 /*
445 * Utility Class
446 */
447 #define I2O_CMD_UTIL_NOP 0x00
448 #define I2O_CMD_UTIL_ABORT 0x01
449 #define I2O_CMD_UTIL_CLAIM 0x09
450 #define I2O_CMD_UTIL_RELEASE 0x0B
451 #define I2O_CMD_UTIL_PARAMS_GET 0x06
452 #define I2O_CMD_UTIL_PARAMS_SET 0x05
453 #define I2O_CMD_UTIL_EVT_REGISTER 0x13
454 #define I2O_CMD_UTIL_EVT_ACK 0x14
455 #define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
456 #define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
457 #define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
458 #define I2O_CMD_UTIL_LOCK 0x17
459 #define I2O_CMD_UTIL_LOCK_RELEASE 0x19
460 #define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
461
462 /*
463 * SCSI Host Bus Adapter Class
464 */
465 #define I2O_CMD_SCSI_EXEC 0x81
466 #define I2O_CMD_SCSI_ABORT 0x83
467 #define I2O_CMD_SCSI_BUSRESET 0x27
468
469 /*
470 * Random Block Storage Class
471 */
472 #define I2O_CMD_BLOCK_READ 0x30
473 #define I2O_CMD_BLOCK_WRITE 0x31
474 #define I2O_CMD_BLOCK_CFLUSH 0x37
475 #define I2O_CMD_BLOCK_MLOCK 0x49
476 #define I2O_CMD_BLOCK_MUNLOCK 0x4B
477 #define I2O_CMD_BLOCK_MMOUNT 0x41
478 #define I2O_CMD_BLOCK_MEJECT 0x43
479 #define I2O_CMD_BLOCK_POWER 0x70
480
481 #define I2O_PRIVATE_MSG 0xFF
482
483 /* Command status values */
484
485 #define I2O_CMD_IN_PROGRESS 0x01
486 #define I2O_CMD_REJECTED 0x02
487 #define I2O_CMD_FAILED 0x03
488 #define I2O_CMD_COMPLETED 0x04
489
490 /* I2O API function return values */
491
492 #define I2O_RTN_NO_ERROR 0
493 #define I2O_RTN_NOT_INIT 1
494 #define I2O_RTN_FREE_Q_EMPTY 2
495 #define I2O_RTN_TCB_ERROR 3
496 #define I2O_RTN_TRANSACTION_ERROR 4
497 #define I2O_RTN_ADAPTER_ALREADY_INIT 5
498 #define I2O_RTN_MALLOC_ERROR 6
499 #define I2O_RTN_ADPTR_NOT_REGISTERED 7
500 #define I2O_RTN_MSG_REPLY_TIMEOUT 8
501 #define I2O_RTN_NO_STATUS 9
502 #define I2O_RTN_NO_FIRM_VER 10
503 #define I2O_RTN_NO_LINK_SPEED 11
504
505 /* Reply message status defines for all messages */
506
507 #define I2O_REPLY_STATUS_SUCCESS 0x00
508 #define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
509 #define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
510 #define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
511 #define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
512 #define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
513 #define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
514 #define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
515 #define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
516 #define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
517 #define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
518 #define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
519
520 /* Status codes and Error Information for Parameter functions */
521
522 #define I2O_PARAMS_STATUS_SUCCESS 0x00
523 #define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
524 #define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
525 #define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
526 #define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
527 #define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
528 #define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
529 #define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
530 #define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
531 #define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
532 #define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
533 #define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
534 #define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
535 #define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
536 #define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
537 #define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
538 #define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
539
540 /* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
541 * messages: Table 3-2 Detailed Status Codes.*/
542
543 #define I2O_DSC_SUCCESS 0x0000
544 #define I2O_DSC_BAD_KEY 0x0002
545 #define I2O_DSC_TCL_ERROR 0x0003
546 #define I2O_DSC_REPLY_BUFFER_FULL 0x0004
547 #define I2O_DSC_NO_SUCH_PAGE 0x0005
548 #define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
549 #define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
550 #define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
551 #define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
552 #define I2O_DSC_DEVICE_LOCKED 0x000B
553 #define I2O_DSC_DEVICE_RESET 0x000C
554 #define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
555 #define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
556 #define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
557 #define I2O_DSC_INVALID_OFFSET 0x0010
558 #define I2O_DSC_INVALID_PARAMETER 0x0011
559 #define I2O_DSC_INVALID_REQUEST 0x0012
560 #define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
561 #define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
562 #define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
563 #define I2O_DSC_MISSING_PARAMETER 0x0016
564 #define I2O_DSC_TIMEOUT 0x0017
565 #define I2O_DSC_UNKNOWN_ERROR 0x0018
566 #define I2O_DSC_UNKNOWN_FUNCTION 0x0019
567 #define I2O_DSC_UNSUPPORTED_VERSION 0x001A
568 #define I2O_DSC_DEVICE_BUSY 0x001B
569 #define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
570
571 /* FailureStatusCodes, Table 3-3 Message Failure Codes */
572
573 #define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
574 #define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
575 #define I2O_FSC_TRANSPORT_CONGESTION 0x83
576 #define I2O_FSC_TRANSPORT_FAILURE 0x84
577 #define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
578 #define I2O_FSC_TRANSPORT_TIME_OUT 0x86
579 #define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
580 #define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
581 #define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
582 #define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
583 #define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
584 #define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
585 #define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
586 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
587 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
588 #define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
589
590 /* Device Claim Types */
591 #define I2O_CLAIM_PRIMARY 0x01000000
592 #define I2O_CLAIM_MANAGEMENT 0x02000000
593 #define I2O_CLAIM_AUTHORIZED 0x03000000
594 #define I2O_CLAIM_SECONDARY 0x04000000
595
596 /* Message header defines for VersionOffset */
597 #define I2OVER15 0x0001
598 #define I2OVER20 0x0002
599
600 /* Default is 1.5, FIXME: Need support for both 1.5 and 2.0 */
601 #define I2OVERSION I2OVER15
602
603 #define SGL_OFFSET_0 I2OVERSION
604 #define SGL_OFFSET_4 (0x0040 | I2OVERSION)
605 #define SGL_OFFSET_5 (0x0050 | I2OVERSION)
606 #define SGL_OFFSET_6 (0x0060 | I2OVERSION)
607 #define SGL_OFFSET_7 (0x0070 | I2OVERSION)
608 #define SGL_OFFSET_8 (0x0080 | I2OVERSION)
609 #define SGL_OFFSET_9 (0x0090 | I2OVERSION)
610 #define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
611
612 #define TRL_OFFSET_5 (0x0050 | I2OVERSION)
613 #define TRL_OFFSET_6 (0x0060 | I2OVERSION)
614
615 /* Transaction Reply Lists (TRL) Control Word structure */
616 #define TRL_SINGLE_FIXED_LENGTH 0x00
617 #define TRL_SINGLE_VARIABLE_LENGTH 0x40
618 #define TRL_MULTIPLE_FIXED_LENGTH 0x80
619
620
621 /* msg header defines for MsgFlags */
622 #define MSG_STATIC 0x0100
623 #define MSG_64BIT_CNTXT 0x0200
624 #define MSG_MULTI_TRANS 0x1000
625 #define MSG_FAIL 0x2000
626 #define MSG_FINAL 0x4000
627 #define MSG_REPLY 0x8000
628
629 /* minimum size msg */
630 #define THREE_WORD_MSG_SIZE 0x00030000
631 #define FOUR_WORD_MSG_SIZE 0x00040000
632 #define FIVE_WORD_MSG_SIZE 0x00050000
633 #define SIX_WORD_MSG_SIZE 0x00060000
634 #define SEVEN_WORD_MSG_SIZE 0x00070000
635 #define EIGHT_WORD_MSG_SIZE 0x00080000
636 #define NINE_WORD_MSG_SIZE 0x00090000
637 #define TEN_WORD_MSG_SIZE 0x000A0000
638 #define ELEVEN_WORD_MSG_SIZE 0x000B0000
639 #define I2O_MESSAGE_SIZE(x) ((x)<<16)
640
641
642 /* Special TID Assignments */
643
644 #define ADAPTER_TID 0
645 #define HOST_TID 1
646
647 #define MSG_FRAME_SIZE 64 /* i2o_scsi assumes >= 32 */
648 #define NMBR_MSG_FRAMES 128
649
650 #define MSG_POOL_SIZE (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32))
651
652 #define I2O_POST_WAIT_OK 0
653 #define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
654
655 #endif /* __KERNEL__ */
656 #endif /* _I2O_H */
657