1 #ifndef __ASM_MPSPEC_H 2 #define __ASM_MPSPEC_H 3 4 /* 5 * Structure definitions for SMP machines following the 6 * Intel Multiprocessing Specification 1.1 and 1.4. 7 */ 8 9 /* 10 * This tag identifies where the SMP configuration 11 * information is. 12 */ 13 14 #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_') 15 16 /* 17 * a maximum of 16 APICs with the current APIC ID architecture. 18 */ 19 #define MAX_APICS 16 20 21 struct intel_mp_floating 22 { 23 char mpf_signature[4]; /* "_MP_" */ 24 unsigned int mpf_physptr; /* Configuration table address */ 25 unsigned char mpf_length; /* Our length (paragraphs) */ 26 unsigned char mpf_specification;/* Specification version */ 27 unsigned char mpf_checksum; /* Checksum (makes sum 0) */ 28 unsigned char mpf_feature1; /* Standard or configuration ? */ 29 unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */ 30 unsigned char mpf_feature3; /* Unused (0) */ 31 unsigned char mpf_feature4; /* Unused (0) */ 32 unsigned char mpf_feature5; /* Unused (0) */ 33 }; 34 35 struct mp_config_table 36 { 37 char mpc_signature[4]; 38 #define MPC_SIGNATURE "PCMP" 39 unsigned short mpc_length; /* Size of table */ 40 char mpc_spec; /* 0x01 */ 41 char mpc_checksum; 42 char mpc_oem[8]; 43 char mpc_productid[12]; 44 unsigned int mpc_oemptr; /* 0 if not present */ 45 unsigned short mpc_oemsize; /* 0 if not present */ 46 unsigned short mpc_oemcount; 47 unsigned int mpc_lapic; /* APIC address */ 48 unsigned int reserved; 49 }; 50 51 /* Followed by entries */ 52 53 #define MP_PROCESSOR 0 54 #define MP_BUS 1 55 #define MP_IOAPIC 2 56 #define MP_INTSRC 3 57 #define MP_LINTSRC 4 58 59 struct mpc_config_processor 60 { 61 unsigned char mpc_type; 62 unsigned char mpc_apicid; /* Local APIC number */ 63 unsigned char mpc_apicver; /* Its versions */ 64 unsigned char mpc_cpuflag; 65 #define CPU_ENABLED 1 /* Processor is available */ 66 #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */ 67 unsigned int mpc_cpufeature; 68 #define CPU_STEPPING_MASK 0x0F 69 #define CPU_MODEL_MASK 0xF0 70 #define CPU_FAMILY_MASK 0xF00 71 unsigned int mpc_featureflag; /* CPUID feature value */ 72 unsigned int mpc_reserved[2]; 73 }; 74 75 struct mpc_config_bus 76 { 77 unsigned char mpc_type; 78 unsigned char mpc_busid; 79 unsigned char mpc_bustype[6]; 80 }; 81 82 /* List of Bus Type string values, Intel MP Spec. */ 83 #define BUSTYPE_EISA "EISA" 84 #define BUSTYPE_ISA "ISA" 85 #define BUSTYPE_INTERN "INTERN" /* Internal BUS */ 86 #define BUSTYPE_MCA "MCA" 87 #define BUSTYPE_VL "VL" /* Local bus */ 88 #define BUSTYPE_PCI "PCI" 89 #define BUSTYPE_PCMCIA "PCMCIA" 90 #define BUSTYPE_CBUS "CBUS" 91 #define BUSTYPE_CBUSII "CBUSII" 92 #define BUSTYPE_FUTURE "FUTURE" 93 #define BUSTYPE_MBI "MBI" 94 #define BUSTYPE_MBII "MBII" 95 #define BUSTYPE_MPI "MPI" 96 #define BUSTYPE_MPSA "MPSA" 97 #define BUSTYPE_NUBUS "NUBUS" 98 #define BUSTYPE_TC "TC" 99 #define BUSTYPE_VME "VME" 100 #define BUSTYPE_XPRESS "XPRESS" 101 102 struct mpc_config_ioapic 103 { 104 unsigned char mpc_type; 105 unsigned char mpc_apicid; 106 unsigned char mpc_apicver; 107 unsigned char mpc_flags; 108 #define MPC_APIC_USABLE 0x01 109 unsigned int mpc_apicaddr; 110 }; 111 112 struct mpc_config_intsrc 113 { 114 unsigned char mpc_type; 115 unsigned char mpc_irqtype; 116 unsigned short mpc_irqflag; 117 unsigned char mpc_srcbus; 118 unsigned char mpc_srcbusirq; 119 unsigned char mpc_dstapic; 120 unsigned char mpc_dstirq; 121 }; 122 123 enum mp_irq_source_types { 124 mp_INT = 0, 125 mp_NMI = 1, 126 mp_SMI = 2, 127 mp_ExtINT = 3 128 }; 129 130 #define MP_IRQDIR_DEFAULT 0 131 #define MP_IRQDIR_HIGH 1 132 #define MP_IRQDIR_LOW 3 133 134 135 struct mpc_config_lintsrc 136 { 137 unsigned char mpc_type; 138 unsigned char mpc_irqtype; 139 unsigned short mpc_irqflag; 140 unsigned char mpc_srcbusid; 141 unsigned char mpc_srcbusirq; 142 unsigned char mpc_destapic; 143 #define MP_APIC_ALL 0xFF 144 unsigned char mpc_destapiclint; 145 }; 146 147 /* 148 * Default configurations 149 * 150 * 1 2 CPU ISA 82489DX 151 * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining 152 * 3 2 CPU EISA 82489DX 153 * 4 2 CPU MCA 82489DX 154 * 5 2 CPU ISA+PCI 155 * 6 2 CPU EISA+PCI 156 * 7 2 CPU MCA+PCI 157 */ 158 159 #define MAX_MP_BUSSES 257 160 #define MAX_IRQ_SOURCES (MAX_MP_BUSSES*4) 161 enum mp_bustype { 162 MP_BUS_ISA = 1, 163 MP_BUS_EISA, 164 MP_BUS_PCI, 165 MP_BUS_MCA 166 }; 167 extern int mp_bus_id_to_type [MAX_MP_BUSSES]; 168 extern int mp_bus_id_to_node [MAX_MP_BUSSES]; 169 extern int mp_bus_id_to_local [MAX_MP_BUSSES]; 170 extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; 171 extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES]; 172 173 extern unsigned int boot_cpu_physical_apicid; 174 extern unsigned long phys_cpu_present_map; 175 extern int smp_found_config; 176 extern void find_smp_config (void); 177 extern void get_smp_config (void); 178 extern int nr_ioapics; 179 extern int apic_version [MAX_APICS]; 180 extern int mp_bus_id_to_type [MAX_MP_BUSSES]; 181 extern int mp_irq_entries; 182 extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES]; 183 extern int mpc_default_type; 184 extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES]; 185 extern int mp_current_pci_id; 186 extern unsigned long mp_lapic_addr; 187 extern int pic_mode; 188 extern int using_apic_timer; 189 190 191 #ifdef CONFIG_ACPI_BOOT 192 extern void mp_register_lapic (u8 id, u8 enabled); 193 extern void mp_register_lapic_address (u64 address); 194 195 #ifdef CONFIG_X86_IO_APIC 196 extern void mp_register_ioapic (u8 id, u32 address, u32 irq_base); 197 extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 global_irq); 198 extern void mp_config_acpi_legacy_irqs (void); 199 extern void mp_parse_prt (void); 200 #endif /*CONFIG_X86_IO_APIC*/ 201 202 #endif /*CONFIG_ACPI_BOOT*/ 203 204 #endif 205 206