1 /* $Id: system.h,v 1.68 2001/11/18 00:12:56 davem Exp $ */
2 #ifndef __SPARC64_SYSTEM_H
3 #define __SPARC64_SYSTEM_H
4
5 #include <linux/config.h>
6 #include <asm/ptrace.h>
7 #include <asm/processor.h>
8 #include <asm/asm_offsets.h>
9 #include <asm/visasm.h>
10
11 #ifndef __ASSEMBLY__
12 /*
13 * Sparc (general) CPU types
14 */
15 enum sparc_cpu {
16 sun4 = 0x00,
17 sun4c = 0x01,
18 sun4m = 0x02,
19 sun4d = 0x03,
20 sun4e = 0x04,
21 sun4u = 0x05, /* V8 ploos ploos */
22 sun_unknown = 0x06,
23 ap1000 = 0x07, /* almost a sun4m */
24 };
25
26 #define sparc_cpu_model sun4u
27
28 /* This cannot ever be a sun4c nor sun4 :) That's just history. */
29 #define ARCH_SUN4C_SUN4 0
30 #define ARCH_SUN4 0
31
32 #endif
33
34 #define setipl(__new_ipl) \
35 __asm__ __volatile__("wrpr %0, %%pil" : : "r" (__new_ipl) : "memory")
36
37 #define __cli() \
38 __asm__ __volatile__("wrpr 15, %%pil" : : : "memory")
39
40 #define __sti() \
41 __asm__ __volatile__("wrpr 0, %%pil" : : : "memory")
42
43 #define getipl() \
44 ({ unsigned long retval; __asm__ __volatile__("rdpr %%pil, %0" : "=r" (retval)); retval; })
45
46 #define swap_pil(__new_pil) \
47 ({ unsigned long retval; \
48 __asm__ __volatile__("rdpr %%pil, %0\n\t" \
49 "wrpr %1, %%pil" \
50 : "=&r" (retval) \
51 : "r" (__new_pil) \
52 : "memory"); \
53 retval; \
54 })
55
56 #define read_pil_and_cli() \
57 ({ unsigned long retval; \
58 __asm__ __volatile__("rdpr %%pil, %0\n\t" \
59 "wrpr 15, %%pil" \
60 : "=r" (retval) \
61 : : "memory"); \
62 retval; \
63 })
64
65 #define read_pil_and_sti() \
66 ({ unsigned long retval; \
67 __asm__ __volatile__("rdpr %%pil, %0\n\t" \
68 "wrpr 0, %%pil" \
69 : "=r" (retval) \
70 : : "memory"); \
71 retval; \
72 })
73
74 #define __save_flags(flags) ((flags) = getipl())
75 #define __save_and_cli(flags) ((flags) = read_pil_and_cli())
76 #define __save_and_sti(flags) ((flags) = read_pil_and_sti())
77 #define __restore_flags(flags) setipl((flags))
78 #define local_irq_disable() __cli()
79 #define local_irq_enable() __sti()
80 #define local_irq_save(flags) __save_and_cli(flags)
81 #define local_irq_set(flags) __save_and_sti(flags)
82 #define local_irq_restore(flags) __restore_flags(flags)
83
84 #ifndef CONFIG_SMP
85 #define cli() __cli()
86 #define sti() __sti()
87 #define save_flags(x) __save_flags(x)
88 #define restore_flags(x) __restore_flags(x)
89 #define save_and_cli(x) __save_and_cli(x)
90 #else
91
92 #ifndef __ASSEMBLY__
93 extern void __global_cli(void);
94 extern void __global_sti(void);
95 extern unsigned long __global_save_flags(void);
96 extern void __global_restore_flags(unsigned long flags);
97 #endif
98
99 #define cli() __global_cli()
100 #define sti() __global_sti()
101 #define save_flags(x) ((x) = __global_save_flags())
102 #define restore_flags(flags) __global_restore_flags(flags)
103 #define save_and_cli(flags) do { save_flags(flags); cli(); } while(0)
104
105 #endif
106
107 #define nop() __asm__ __volatile__ ("nop")
108
109 /* These are here in an effort to more fully work around Spitfire Errata
110 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
111 * branch, the chip can stop executing instructions until a trap occurs.
112 * Therefore, if interrupts are disabled, the chip can hang forever.
113 *
114 * It used to be believed that the memory barrier had to be right in the
115 * delay slot, but a case has been traced recently wherein the memory barrier
116 * was one instruction after the branch delay slot and the chip still hung.
117 * The offending sequence was the following in sym_wakeup_done() of the
118 * sym53c8xx_2 driver:
119 *
120 * call sym_ccb_from_dsa, 0
121 * movge %icc, 0, %l0
122 * brz,pn %o0, .LL1303
123 * mov %o0, %l2
124 * membar #LoadLoad
125 *
126 * The branch has to be mispredicted for the bug to occur. Therefore, we put
127 * the memory barrier explicitly into a "branch always, predicted taken"
128 * delay slot to avoid the problem case.
129 */
130 #define membar_safe(type) \
131 do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
132 " membar " type "\n" \
133 "1:\n" \
134 : : : "memory"); \
135 } while (0)
136 #define mb() \
137 membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
138 #define rmb() \
139 membar_safe("#LoadLoad")
140 #define wmb() \
141 membar_safe("#StoreStore")
142 #define set_mb(__var, __value) \
143 do { __var = __value; \
144 membar_safe("#StoreLoad | #StoreStore"); \
145 } while(0)
146 #define set_wmb(__var, __value) \
147 do { __var = __value; \
148 membar_safe("#StoreStore"); \
149 } while(0)
150
151 #ifdef CONFIG_SMP
152 #define smp_mb() mb()
153 #define smp_rmb() rmb()
154 #define smp_wmb() wmb()
155 #else
156 #define smp_mb() __asm__ __volatile__("":::"memory")
157 #define smp_rmb() __asm__ __volatile__("":::"memory")
158 #define smp_wmb() __asm__ __volatile__("":::"memory")
159 #endif
160
161 #define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
162
163 #define flushw_all() __asm__ __volatile__("flushw")
164
165 /* Performance counter register access. */
166 #define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
167 #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p));
168 #define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
169
170 /* Blackbird errata workaround. See commentary in
171 * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
172 * for more information.
173 */
174 #define reset_pic() \
175 __asm__ __volatile__("ba,pt %xcc, 99f\n\t" \
176 ".align 64\n" \
177 "99:wr %g0, 0x0, %pic\n\t" \
178 "rd %pic, %g0")
179
180 #ifndef __ASSEMBLY__
181
182 extern void synchronize_user_stack(void);
183
184 extern void __flushw_user(void);
185 #define flushw_user() __flushw_user()
186
187 #define flush_user_windows flushw_user
188 #define flush_register_windows flushw_all
189 #define prepare_to_switch flushw_all
190
191 #ifndef CONFIG_DEBUG_SPINLOCK
192 #define CHECK_LOCKS(PREV) do { } while(0)
193 #else /* CONFIG_DEBUG_SPINLOCK */
194 #define CHECK_LOCKS(PREV) \
195 if ((PREV)->thread.smp_lock_count) { \
196 unsigned long rpc; \
197 __asm__ __volatile__("mov %%i7, %0" : "=r" (rpc)); \
198 printk(KERN_CRIT "(%s)[%d]: Sleeping with %d locks held!\n", \
199 (PREV)->comm, (PREV)->pid, \
200 (PREV)->thread.smp_lock_count); \
201 printk(KERN_CRIT "(%s)[%d]: Last lock at %08x\n", \
202 (PREV)->comm, (PREV)->pid, \
203 (PREV)->thread.smp_lock_pc); \
204 printk(KERN_CRIT "(%s)[%d]: Sched caller %016lx\n", \
205 (PREV)->comm, (PREV)->pid, rpc); \
206 }
207 #endif /* !(CONFIG_DEBUG_SPINLOCK) */
208
209 /* See what happens when you design the chip correctly?
210 *
211 * We tell gcc we clobber all non-fixed-usage registers except
212 * for l0/l1. It will use one for 'next' and the other to hold
213 * the output value of 'last'. 'next' is not referenced again
214 * past the invocation of switch_to in the scheduler, so we need
215 * not preserve it's value. Hairy, but it lets us remove 2 loads
216 * and 2 stores in this critical code path. -DaveM
217 */
218 #define switch_to(prev, next, last) \
219 do { CHECK_LOCKS(prev); \
220 if (current->thread.flags & SPARC_FLAG_PERFCTR) { \
221 unsigned long __tmp; \
222 read_pcr(__tmp); \
223 current->thread.pcr_reg = __tmp; \
224 read_pic(__tmp); \
225 current->thread.kernel_cntd0 += (unsigned int)(__tmp); \
226 current->thread.kernel_cntd1 += ((__tmp) >> 32); \
227 } \
228 save_and_clear_fpu(); \
229 /* If you are tempted to conditionalize the following */ \
230 /* so that ASI is only written if it changes, think again. */ \
231 __asm__ __volatile__("wr %%g0, %0, %%asi" \
232 : : "r" (next->thread.current_ds.seg)); \
233 __asm__ __volatile__( \
234 "mov %%g6, %%g5\n\t" \
235 "wrpr %%g0, 0x95, %%pstate\n\t" \
236 "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
237 "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
238 "rdpr %%wstate, %%o5\n\t" \
239 "stx %%o6, [%%g6 + %3]\n\t" \
240 "stb %%o5, [%%g6 + %2]\n\t" \
241 "rdpr %%cwp, %%o5\n\t" \
242 "stb %%o5, [%%g6 + %5]\n\t" \
243 "mov %1, %%g6\n\t" \
244 "ldub [%1 + %5], %%g1\n\t" \
245 "wrpr %%g1, %%cwp\n\t" \
246 "ldx [%%g6 + %3], %%o6\n\t" \
247 "ldub [%%g6 + %2], %%o5\n\t" \
248 "ldub [%%g6 + %4], %%o7\n\t" \
249 "mov %%g6, %%l2\n\t" \
250 "wrpr %%o5, 0x0, %%wstate\n\t" \
251 "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
252 "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
253 "wrpr %%g0, 0x94, %%pstate\n\t" \
254 "mov %%l2, %%g6\n\t" \
255 "wrpr %%g0, 0x96, %%pstate\n\t" \
256 "andcc %%o7, %6, %%g0\n\t" \
257 "bne,pn %%icc, ret_from_syscall\n\t" \
258 " mov %%g5, %0\n\t" \
259 : "=&r" (last) \
260 : "r" (next), \
261 "i" ((const unsigned long)(&((struct task_struct *)0)->thread.wstate)),\
262 "i" ((const unsigned long)(&((struct task_struct *)0)->thread.ksp)), \
263 "i" ((const unsigned long)(&((struct task_struct *)0)->thread.flags)),\
264 "i" ((const unsigned long)(&((struct task_struct *)0)->thread.cwp)), \
265 "i" (SPARC_FLAG_NEWCHILD) \
266 : "cc", \
267 "g1", "g2", "g3", "g5", "g7", \
268 "l2", "l3", "l4", "l5", "l6", "l7", \
269 "i0", "i1", "i2", "i3", "i4", "i5", \
270 "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \
271 /* If you fuck with this, update ret_from_syscall code too. */ \
272 if (current->thread.flags & SPARC_FLAG_PERFCTR) { \
273 write_pcr(current->thread.pcr_reg); \
274 reset_pic(); \
275 } \
276 } while(0)
277
xchg32(__volatile__ unsigned int * m,unsigned int val)278 extern __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
279 {
280 __asm__ __volatile__(
281 " membar #StoreLoad | #LoadLoad\n"
282 " mov %0, %%g5\n"
283 "1: lduw [%2], %%g7\n"
284 " cas [%2], %%g7, %0\n"
285 " cmp %%g7, %0\n"
286 " bne,a,pn %%icc, 1b\n"
287 " mov %%g5, %0\n"
288 " membar #StoreLoad | #StoreStore\n"
289 : "=&r" (val)
290 : "0" (val), "r" (m)
291 : "g5", "g7", "cc", "memory");
292 return val;
293 }
294
xchg64(__volatile__ unsigned long * m,unsigned long val)295 extern __inline__ unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
296 {
297 __asm__ __volatile__(
298 " membar #StoreLoad | #LoadLoad\n"
299 " mov %0, %%g5\n"
300 "1: ldx [%2], %%g7\n"
301 " casx [%2], %%g7, %0\n"
302 " cmp %%g7, %0\n"
303 " bne,a,pn %%xcc, 1b\n"
304 " mov %%g5, %0\n"
305 " membar #StoreLoad | #StoreStore\n"
306 : "=&r" (val)
307 : "0" (val), "r" (m)
308 : "g5", "g7", "cc", "memory");
309 return val;
310 }
311
312 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
313 #define tas(ptr) (xchg((ptr),1))
314
315 extern void __xchg_called_with_bad_pointer(void);
316
__xchg(unsigned long x,__volatile__ void * ptr,int size)317 static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
318 int size)
319 {
320 switch (size) {
321 case 4:
322 return xchg32(ptr, x);
323 case 8:
324 return xchg64(ptr, x);
325 };
326 __xchg_called_with_bad_pointer();
327 return x;
328 }
329
330 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
331
332 /*
333 * Atomic compare and exchange. Compare OLD with MEM, if identical,
334 * store NEW in MEM. Return the initial value in MEM. Success is
335 * indicated by comparing RETURN with OLD.
336 */
337
338 #define __HAVE_ARCH_CMPXCHG 1
339
340 extern __inline__ unsigned long
__cmpxchg_u32(volatile int * m,int old,int new)341 __cmpxchg_u32(volatile int *m, int old, int new)
342 {
343 __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
344 "cas [%2], %3, %0\n\t"
345 "membar #StoreLoad | #StoreStore"
346 : "=&r" (new)
347 : "0" (new), "r" (m), "r" (old)
348 : "memory");
349
350 return new;
351 }
352
353 extern __inline__ unsigned long
__cmpxchg_u64(volatile long * m,unsigned long old,unsigned long new)354 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
355 {
356 __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
357 "casx [%2], %3, %0\n\t"
358 "membar #StoreLoad | #StoreStore"
359 : "=&r" (new)
360 : "0" (new), "r" (m), "r" (old)
361 : "memory");
362
363 return new;
364 }
365
366 /* This function doesn't exist, so you'll get a linker error
367 if something tries to do an invalid cmpxchg(). */
368 extern void __cmpxchg_called_with_bad_pointer(void);
369
370 static __inline__ unsigned long
__cmpxchg(volatile void * ptr,unsigned long old,unsigned long new,int size)371 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
372 {
373 switch (size) {
374 case 4:
375 return __cmpxchg_u32(ptr, old, new);
376 case 8:
377 return __cmpxchg_u64(ptr, old, new);
378 }
379 __cmpxchg_called_with_bad_pointer();
380 return old;
381 }
382
383 #define cmpxchg(ptr,o,n) \
384 ({ \
385 __typeof__(*(ptr)) _o_ = (o); \
386 __typeof__(*(ptr)) _n_ = (n); \
387 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
388 (unsigned long)_n_, sizeof(*(ptr))); \
389 })
390
391 #endif /* !(__ASSEMBLY__) */
392
393 #endif /* !(__SPARC64_SYSTEM_H) */
394