1 /* $Id: sab82532.h,v 1.7 2001/05/23 23:09:10 ecd Exp $
2  * sab82532.h: Register Definitions for the Siemens SAB82532 DUSCC
3  *
4  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
5  */
6 
7 #ifndef _SPARC64_SAB82532_H
8 #define _SPARC64_SAB82532_H
9 
10 #include <linux/types.h>
11 #include <linux/serial.h>
12 #include <linux/circ_buf.h>
13 
14 struct sab82532_async_rd_regs {
15 	u8	rfifo[0x20];	/* Receive FIFO				*/
16 	u8	star;		/* Status Register			*/
17 	u8	__pad1;
18 	u8	mode;		/* Mode Register			*/
19 	u8	timr;		/* Timer Register			*/
20 	u8	xon;		/* XON Character			*/
21 	u8	xoff;		/* XOFF Character			*/
22 	u8	tcr;		/* Termination Character Register	*/
23 	u8	dafo;		/* Data Format				*/
24 	u8	rfc;		/* RFIFO Control Register		*/
25 	u8	__pad2;
26 	u8	rbcl;		/* Receive Byte Count Low		*/
27 	u8	rbch;		/* Receive Byte Count High		*/
28 	u8	ccr0;		/* Channel Configuration Register 0	*/
29 	u8	ccr1;		/* Channel Configuration Register 1	*/
30 	u8	ccr2;		/* Channel Configuration Register 2	*/
31 	u8	ccr3;		/* Channel Configuration Register 3	*/
32 	u8	__pad3[4];
33 	u8	vstr;		/* Version Status Register		*/
34 	u8	__pad4[3];
35 	u8	gis;		/* Global Interrupt Status		*/
36 	u8	ipc;		/* Interrupt Port Configuration		*/
37 	u8	isr0;		/* Interrupt Status 0			*/
38 	u8	isr1;		/* Interrupt Status 1			*/
39 	u8	pvr;		/* Port Value Register			*/
40 	u8	pis;		/* Port Interrupt Status		*/
41 	u8	pcr;		/* Port Configuration Register		*/
42 	u8	ccr4;		/* Channel Configuration Register 4	*/
43 };
44 
45 struct sab82532_async_wr_regs {
46 	u8	xfifo[0x20];	/* Transmit FIFO			*/
47 	u8	cmdr;		/* Command Register			*/
48 	u8	__pad1;
49 	u8	mode;
50 	u8	timr;
51 	u8	xon;
52 	u8	xoff;
53 	u8	tcr;
54 	u8	dafo;
55 	u8	rfc;
56 	u8	__pad2;
57 	u8	xbcl;		/* Transmit Byte Count Low		*/
58 	u8	xbch;		/* Transmit Byte Count High		*/
59 	u8	ccr0;
60 	u8	ccr1;
61 	u8	ccr2;
62 	u8	ccr3;
63 	u8	tsax;		/* Time-Slot Assignment Reg. Transmit	*/
64 	u8	tsar;		/* Time-Slot Assignment Reg. Receive	*/
65 	u8	xccr;		/* Transmit Channel Capacity Register	*/
66 	u8	rccr;		/* Receive Channel Capacity Register	*/
67 	u8	bgr;		/* Baud Rate Generator Register		*/
68 	u8	tic;		/* Transmit Immediate Character		*/
69 	u8	mxn;		/* Mask XON Character			*/
70 	u8	mxf;		/* Mask XOFF Character			*/
71 	u8	iva;		/* Interrupt Vector Address		*/
72 	u8	ipc;
73 	u8	imr0;		/* Interrupt Mask Register 0		*/
74 	u8	imr1;		/* Interrupt Mask Register 1		*/
75 	u8	pvr;
76 	u8	pim;		/* Port Interrupt Mask			*/
77 	u8	pcr;
78 	u8	ccr4;
79 };
80 
81 struct sab82532_async_rw_regs {	/* Read/Write registers			*/
82 	u8	__pad1[0x20];
83 	u8	__pad2;
84 	u8	__pad3;
85 	u8	mode;
86 	u8	timr;
87 	u8	xon;
88 	u8	xoff;
89 	u8	tcr;
90 	u8	dafo;
91 	u8	rfc;
92 	u8	__pad4;
93 	u8	__pad5;
94 	u8	__pad6;
95 	u8	ccr0;
96 	u8	ccr1;
97 	u8	ccr2;
98 	u8	ccr3;
99 	u8	__pad7;
100 	u8	__pad8;
101 	u8	__pad9;
102 	u8	__pad10;
103 	u8	__pad11;
104 	u8	__pad12;
105 	u8	__pad13;
106 	u8	__pad14;
107 	u8	__pad15;
108 	u8	ipc;
109 	u8	__pad16;
110 	u8	__pad17;
111 	u8	pvr;
112 	u8	__pad18;
113 	u8	pcr;
114 	u8	ccr4;
115 };
116 
117 union sab82532_async_regs {
118 	__volatile__ struct sab82532_async_rd_regs	r;
119 	__volatile__ struct sab82532_async_wr_regs	w;
120 	__volatile__ struct sab82532_async_rw_regs	rw;
121 };
122 
123 #define NR_PORTS			 2
124 
125 union sab82532_irq_status {
126 	unsigned short			 stat;
127 	struct {
128 		unsigned char		 isr0;
129 		unsigned char		 isr1;
130 	} sreg;
131 };
132 
133 struct sab82532 {
134 	int				 magic;
135 	int				 baud_base;
136 	union sab82532_async_regs	*regs;
137 	int				 irq;
138 	int				 flags;		/* defined in tty.h */
139 	int				 type;		/* SAB82532 version */
140 	struct tty_struct		*tty;
141 	int				 read_status_mask;
142 	int				 ignore_status_mask;
143 	int				 timeout;
144 	int				 xmit_fifo_size;
145 	int				 recv_fifo_size;
146 	int				 custom_divisor;
147 	int				 baud;
148 	unsigned int			 cec_timeout;
149 	unsigned int			 tec_timeout;
150 	int				 x_char;
151 	int				 close_delay;
152 	unsigned short			 closing_wait;
153 	unsigned short			 closing_wait2;
154 	unsigned long			 irqflags;
155 	int				 is_console;
156 	unsigned char			 interrupt_mask0;
157 	unsigned char			 interrupt_mask1;
158 	unsigned char			 pvr_dtr_bit;
159 	unsigned char			 pvr_dsr_bit;
160 	unsigned char			 dcd;
161 	unsigned char			 cts;
162 	unsigned char			 dsr;
163 	unsigned long			 event;
164 	unsigned long			 last_active;
165 	int				 line;
166 	int				 count;
167 	int				 blocked_open;
168 	long				 session;
169 	long				 pgrp;
170 	struct circ_buf			 xmit;
171 	struct tq_struct		 tqueue;
172 	struct tq_struct		 tqueue_hangup;
173 	struct async_icount		 icount;
174 	struct termios			 normal_termios;
175 	struct termios			 callout_termios;
176 	wait_queue_head_t		 open_wait;
177 	wait_queue_head_t		 close_wait;
178 	wait_queue_head_t		 delta_msr_wait;
179 	struct sab82532			*next;
180 	struct sab82532			*prev;
181 };
182 
183 
184 /* irqflags bits */
185 #define SAB82532_ALLS			0x00000001
186 #define SAB82532_XPR			0x00000002
187 
188 
189 /* RFIFO Status Byte */
190 #define SAB82532_RSTAT_PE		0x80
191 #define SAB82532_RSTAT_FE		0x40
192 #define SAB82532_RSTAT_PARITY		0x01
193 
194 /* Status Register (STAR) */
195 #define SAB82532_STAR_XDOV		0x80
196 #define SAB82532_STAR_XFW		0x40
197 #define SAB82532_STAR_RFNE		0x20
198 #define SAB82532_STAR_FCS		0x10
199 #define SAB82532_STAR_TEC		0x08
200 #define SAB82532_STAR_CEC		0x04
201 #define SAB82532_STAR_CTS		0x02
202 
203 /* Command Register (CMDR) */
204 #define SAB82532_CMDR_RMC		0x80
205 #define SAB82532_CMDR_RRES		0x40
206 #define SAB82532_CMDR_RFRD		0x20
207 #define SAB82532_CMDR_STI		0x10
208 #define SAB82532_CMDR_XF		0x08
209 #define SAB82532_CMDR_XRES		0x01
210 
211 /* Mode Register (MODE) */
212 #define SAB82532_MODE_FRTS		0x40
213 #define SAB82532_MODE_FCTS		0x20
214 #define SAB82532_MODE_FLON		0x10
215 #define SAB82532_MODE_RAC		0x08
216 #define SAB82532_MODE_RTS		0x04
217 #define SAB82532_MODE_TRS		0x02
218 #define SAB82532_MODE_TLP		0x01
219 
220 /* Timer Register (TIMR) */
221 #define SAB82532_TIMR_CNT_MASK		0xe0
222 #define SAB82532_TIMR_VALUE_MASK	0x1f
223 
224 /* Data Format (DAFO) */
225 #define SAB82532_DAFO_XBRK		0x40
226 #define SAB82532_DAFO_STOP		0x20
227 #define SAB82532_DAFO_PAR_SPACE		0x00
228 #define SAB82532_DAFO_PAR_ODD		0x08
229 #define SAB82532_DAFO_PAR_EVEN		0x10
230 #define SAB82532_DAFO_PAR_MARK		0x18
231 #define SAB82532_DAFO_PARE		0x04
232 #define SAB82532_DAFO_CHL8		0x00
233 #define SAB82532_DAFO_CHL7		0x01
234 #define SAB82532_DAFO_CHL6		0x02
235 #define SAB82532_DAFO_CHL5		0x03
236 
237 /* RFIFO Control Register (RFC) */
238 #define SAB82532_RFC_DPS		0x40
239 #define SAB82532_RFC_DXS		0x20
240 #define SAB82532_RFC_RFDF		0x10
241 #define SAB82532_RFC_RFTH_1		0x00
242 #define SAB82532_RFC_RFTH_4		0x04
243 #define SAB82532_RFC_RFTH_16		0x08
244 #define SAB82532_RFC_RFTH_32		0x0c
245 #define SAB82532_RFC_TCDE		0x01
246 
247 /* Received Byte Count High (RBCH) */
248 #define SAB82532_RBCH_DMA		0x80
249 #define SAB82532_RBCH_CAS		0x20
250 
251 /* Transmit Byte Count High (XBCH) */
252 #define SAB82532_XBCH_DMA		0x80
253 #define SAB82532_XBCH_CAS		0x20
254 #define SAB82532_XBCH_XC		0x10
255 
256 /* Channel Configuration Register 0 (CCR0) */
257 #define SAB82532_CCR0_PU		0x80
258 #define SAB82532_CCR0_MCE		0x40
259 #define SAB82532_CCR0_SC_NRZ		0x00
260 #define SAB82532_CCR0_SC_NRZI		0x08
261 #define SAB82532_CCR0_SC_FM0		0x10
262 #define SAB82532_CCR0_SC_FM1		0x14
263 #define SAB82532_CCR0_SC_MANCH		0x18
264 #define SAB82532_CCR0_SM_HDLC		0x00
265 #define SAB82532_CCR0_SM_SDLC_LOOP	0x01
266 #define SAB82532_CCR0_SM_BISYNC		0x02
267 #define SAB82532_CCR0_SM_ASYNC		0x03
268 
269 /* Channel Configuration Register 1 (CCR1) */
270 #define SAB82532_CCR1_ODS		0x10
271 #define SAB82532_CCR1_BCR		0x08
272 #define SAB82532_CCR1_CM_MASK		0x07
273 
274 /* Channel Configuration Register 2 (CCR2) */
275 #define SAB82532_CCR2_SOC1		0x80
276 #define SAB82532_CCR2_SOC0		0x40
277 #define SAB82532_CCR2_BR9		0x80
278 #define SAB82532_CCR2_BR8		0x40
279 #define SAB82532_CCR2_BDF		0x20
280 #define SAB82532_CCR2_SSEL		0x10
281 #define SAB82532_CCR2_XCS0		0x20
282 #define SAB82532_CCR2_RCS0		0x10
283 #define SAB82532_CCR2_TOE		0x08
284 #define SAB82532_CCR2_RWX		0x04
285 #define SAB82532_CCR2_DIV		0x01
286 
287 /* Channel Configuration Register 3 (CCR3) */
288 #define SAB82532_CCR3_PSD		0x01
289 
290 /* Time Slot Assignment Register Transmit (TSAX) */
291 #define SAB82532_TSAX_TSNX_MASK		0xfc
292 #define SAB82532_TSAX_XCS2		0x02	/* see also CCR2 */
293 #define SAB82532_TSAX_XCS1		0x01
294 
295 /* Time Slot Assignment Register Receive (TSAR) */
296 #define SAB82532_TSAR_TSNR_MASK		0xfc
297 #define SAB82532_TSAR_RCS2		0x02	/* see also CCR2 */
298 #define SAB82532_TSAR_RCS1		0x01
299 
300 /* Version Status Register (VSTR) */
301 #define SAB82532_VSTR_CD		0x80
302 #define SAB82532_VSTR_DPLA		0x40
303 #define SAB82532_VSTR_VN_MASK		0x0f
304 #define SAB82532_VSTR_VN_1		0x00
305 #define SAB82532_VSTR_VN_2		0x01
306 #define SAB82532_VSTR_VN_3_2		0x02
307 
308 /* Global Interrupt Status Register (GIS) */
309 #define SAB82532_GIS_PI			0x80
310 #define SAB82532_GIS_ISA1		0x08
311 #define SAB82532_GIS_ISA0		0x04
312 #define SAB82532_GIS_ISB1		0x02
313 #define SAB82532_GIS_ISB0		0x01
314 
315 /* Interrupt Vector Address (IVA) */
316 #define SAB82532_IVA_MASK		0xf1
317 
318 /* Interrupt Port Configuration (IPC) */
319 #define SAB82532_IPC_VIS		0x80
320 #define SAB82532_IPC_SLA1		0x10
321 #define SAB82532_IPC_SLA0		0x08
322 #define SAB82532_IPC_CASM		0x04
323 #define SAB82532_IPC_IC_OPEN_DRAIN	0x00
324 #define SAB82532_IPC_IC_ACT_LOW		0x01
325 #define SAB82532_IPC_IC_ACT_HIGH	0x03
326 
327 /* Interrupt Status Register 0 (ISR0) */
328 #define SAB82532_ISR0_TCD		0x80
329 #define SAB82532_ISR0_TIME		0x40
330 #define SAB82532_ISR0_PERR		0x20
331 #define SAB82532_ISR0_FERR		0x10
332 #define SAB82532_ISR0_PLLA		0x08
333 #define SAB82532_ISR0_CDSC		0x04
334 #define SAB82532_ISR0_RFO		0x02
335 #define SAB82532_ISR0_RPF		0x01
336 
337 /* Interrupt Status Register 1 (ISR1) */
338 #define SAB82532_ISR1_BRK		0x80
339 #define SAB82532_ISR1_BRKT		0x40
340 #define SAB82532_ISR1_ALLS		0x20
341 #define SAB82532_ISR1_XOFF		0x10
342 #define SAB82532_ISR1_TIN		0x08
343 #define SAB82532_ISR1_CSC		0x04
344 #define SAB82532_ISR1_XON		0x02
345 #define SAB82532_ISR1_XPR		0x01
346 
347 /* Interrupt Mask Register 0 (IMR0) */
348 #define SAB82532_IMR0_TCD		0x80
349 #define SAB82532_IMR0_TIME		0x40
350 #define SAB82532_IMR0_PERR		0x20
351 #define SAB82532_IMR0_FERR		0x10
352 #define SAB82532_IMR0_PLLA		0x08
353 #define SAB82532_IMR0_CDSC		0x04
354 #define SAB82532_IMR0_RFO		0x02
355 #define SAB82532_IMR0_RPF		0x01
356 
357 /* Interrupt Mask Register 1 (IMR1) */
358 #define SAB82532_IMR1_BRK		0x80
359 #define SAB82532_IMR1_BRKT		0x40
360 #define SAB82532_IMR1_ALLS		0x20
361 #define SAB82532_IMR1_XOFF		0x10
362 #define SAB82532_IMR1_TIN		0x08
363 #define SAB82532_IMR1_CSC		0x04
364 #define SAB82532_IMR1_XON		0x02
365 #define SAB82532_IMR1_XPR		0x01
366 
367 /* Port Interrupt Status Register (PIS) */
368 #define SAB82532_PIS_SYNC_B		0x08
369 #define SAB82532_PIS_DTR_B		0x04
370 #define SAB82532_PIS_DTR_A		0x02
371 #define SAB82532_PIS_SYNC_A		0x01
372 
373 /* Channel Configuration Register 4 (CCR4) */
374 #define SAB82532_CCR4_MCK4		0x80
375 #define SAB82532_CCR4_EBRG		0x40
376 #define SAB82532_CCR4_TST1		0x20
377 #define SAB82532_CCR4_ICD		0x10
378 
379 
380 #endif /* !(_SPARC64_SAB82532_H) */
381