1 /* $Id: ide.h,v 1.21 2001/09/25 20:21:48 kanoj Exp $
2 * ide.h: Ultra/PCI specific IDE glue.
3 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 */
7
8 #ifndef _SPARC64_IDE_H
9 #define _SPARC64_IDE_H
10
11 #ifdef __KERNEL__
12
13 #include <linux/config.h>
14 #include <asm/pgalloc.h>
15 #include <asm/io.h>
16 #include <asm/hdreg.h>
17 #include <asm/page.h>
18 #include <asm/spitfire.h>
19
20 #ifndef MAX_HWIFS
21 # ifdef CONFIG_BLK_DEV_IDEPCI
22 #define MAX_HWIFS 10
23 # else
24 #define MAX_HWIFS 2
25 # endif
26 #endif
27
ide_default_irq(ide_ioreg_t base)28 static __inline__ int ide_default_irq(ide_ioreg_t base)
29 {
30 return 0;
31 }
32
ide_default_io_base(int index)33 static __inline__ ide_ioreg_t ide_default_io_base(int index)
34 {
35 return 0;
36 }
37
ide_init_hwif_ports(hw_regs_t * hw,ide_ioreg_t data_port,ide_ioreg_t ctrl_port,int * irq)38 static __inline__ void ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, ide_ioreg_t ctrl_port, int *irq)
39 {
40 ide_ioreg_t reg = data_port;
41 int i;
42
43 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
44 hw->io_ports[i] = reg;
45 reg += 1;
46 }
47 if (ctrl_port) {
48 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
49 } else {
50 hw->io_ports[IDE_CONTROL_OFFSET] = 0;
51 }
52 if (irq != NULL)
53 *irq = 0;
54 hw->io_ports[IDE_IRQ_OFFSET] = 0;
55 }
56
57 /*
58 * This registers the standard ports for this architecture with the IDE
59 * driver.
60 */
ide_init_default_hwifs(void)61 static __inline__ void ide_init_default_hwifs(void)
62 {
63 #ifndef CONFIG_BLK_DEV_IDEPCI
64 hw_regs_t hw;
65 int index;
66
67 for (index = 0; index < MAX_HWIFS; index++) {
68 ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL);
69 hw.irq = ide_default_irq(ide_default_io_base(index));
70 ide_register_hw(&hw, NULL);
71 }
72 #endif /* CONFIG_BLK_DEV_IDEPCI */
73 }
74
75 #undef SUPPORT_SLOW_DATA_PORTS
76 #define SUPPORT_SLOW_DATA_PORTS 0
77
78 #undef SUPPORT_VLB_SYNC
79 #define SUPPORT_VLB_SYNC 0
80
81 #undef HD_DATA
82 #define HD_DATA ((ide_ioreg_t)0)
83
84 #define __ide_insl(data_reg, buffer, wcount) \
85 __ide_insw(data_reg, buffer, (wcount)<<1)
86 #define __ide_outsl(data_reg, buffer, wcount) \
87 __ide_outsw(data_reg, buffer, (wcount)<<1)
88
89 /* On sparc64, I/O ports and MMIO registers are accessed identically. */
90 #define __ide_mm_insw __ide_insw
91 #define __ide_mm_insl __ide_insl
92 #define __ide_mm_outsw __ide_outsw
93 #define __ide_mm_outsl __ide_outsl
94
inw_be(unsigned long addr)95 static __inline__ unsigned int inw_be(unsigned long addr)
96 {
97 unsigned int ret;
98
99 __asm__ __volatile__("lduha [%1] %2, %0"
100 : "=r" (ret)
101 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
102
103 return ret;
104 }
105
__ide_insw(unsigned long port,void * dst,u32 count)106 static __inline__ void __ide_insw(unsigned long port,
107 void *dst,
108 u32 count)
109 {
110 #if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
111 unsigned long end = (unsigned long)dst + (count << 1);
112 #endif
113 u16 *ps = dst;
114 u32 *pi;
115
116 if(((u64)ps) & 0x2) {
117 *ps++ = inw_be(port);
118 count--;
119 }
120 pi = (u32 *)ps;
121 while(count >= 2) {
122 u32 w;
123
124 w = inw_be(port) << 16;
125 w |= inw_be(port);
126 *pi++ = w;
127 count -= 2;
128 }
129 ps = (u16 *)pi;
130 if(count)
131 *ps++ = inw_be(port);
132
133 #if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
134 __flush_dcache_range((unsigned long)dst, end);
135 #endif
136 }
137
outw_be(unsigned short w,unsigned long addr)138 static __inline__ void outw_be(unsigned short w, unsigned long addr)
139 {
140 __asm__ __volatile__("stha %0, [%1] %2"
141 : /* no outputs */
142 : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
143 }
144
__ide_outsw(unsigned long port,void * src,u32 count)145 static __inline__ void __ide_outsw(unsigned long port,
146 void *src,
147 u32 count)
148 {
149 #if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
150 unsigned long end = (unsigned long)src + (count << 1);
151 #endif
152 const u16 *ps = src;
153 const u32 *pi;
154
155 if(((u64)src) & 0x2) {
156 outw_be(*ps++, port);
157 count--;
158 }
159 pi = (const u32 *)ps;
160 while(count >= 2) {
161 u32 w;
162
163 w = *pi++;
164 outw_be((w >> 16), port);
165 outw_be(w, port);
166 count -= 2;
167 }
168 ps = (const u16 *)pi;
169 if(count)
170 outw_be(*ps, port);
171
172 #if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
173 __flush_dcache_range((unsigned long)src, end);
174 #endif
175 }
176
177 #endif /* __KERNEL__ */
178
179 #endif /* _SPARC64_IDE_H */
180