1 /* 2 * Low-Level PCI Support for SH7751 targets 3 * 4 * Dustin McIntire (dustin@sensoria.com) (c) 2001 5 * 6 * May be copied or modified under the terms of the GNU General Public 7 * License. See linux/COPYING for more information. 8 * 9 */ 10 11 #ifndef _PCI_SH7751_H_ 12 #define _PCI_SH7751_H_ 13 14 #include <linux/pci.h> 15 16 /* set debug level 4=verbose...1=terse */ 17 //#define DEBUG_PCI 3 18 #undef DEBUG_PCI 19 20 #ifdef DEBUG_PCI 21 #define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); } 22 #else 23 #define PCIDBG(n, x...) 24 #endif 25 26 /* startup values */ 27 #define PCI_PROBE_BIOS 1 28 #define PCI_PROBE_CONF1 2 29 #define PCI_PROBE_CONF2 4 30 #define PCI_NO_SORT 0x100 31 #define PCI_BIOS_SORT 0x200 32 #define PCI_NO_CHECKS 0x400 33 #define PCI_ASSIGN_ROMS 0x1000 34 #define PCI_BIOS_IRQ_SCAN 0x2000 35 36 /* Platform Specific Values */ 37 #define SH7751_VENDOR_ID 0x1054 38 #define SH7751_DEVICE_ID 0x3505 39 #define SH7751R_DEVICE_ID 0x350e 40 41 /* SH7751 Specific Values */ 42 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 43 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */ 44 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */ 45 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 46 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */ 47 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */ 48 49 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */ 50 #define PCI_REG(n) (SH7751_PCIREG_BASE+ n) 51 52 #define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */ 53 #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */ 54 #define SH7751_PCICONF0_VNDID 0x0000FFFF /* Vendor ID */ 55 #define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */ 56 #define SH7751_PCICONF1_DPE 0x80000000 /* Data Parity Error */ 57 #define SH7751_PCICONF1_SSE 0x40000000 /* System Error Status */ 58 #define SH7751_PCICONF1_RMA 0x20000000 /* Master Abort */ 59 #define SH7751_PCICONF1_RTA 0x10000000 /* Target Abort Rx Status */ 60 #define SH7751_PCICONF1_STA 0x08000000 /* Target Abort Exec Status */ 61 #define SH7751_PCICONF1_DEV 0x06000000 /* Timing Status */ 62 #define SH7751_PCICONF1_DPD 0x01000000 /* Data Parity Status */ 63 #define SH7751_PCICONF1_FBBC 0x00800000 /* Back 2 Back Status */ 64 #define SH7751_PCICONF1_UDF 0x00400000 /* User Defined Status */ 65 #define SH7751_PCICONF1_66M 0x00200000 /* 66Mhz Operation Status */ 66 #define SH7751_PCICONF1_PM 0x00100000 /* Power Management Status */ 67 #define SH7751_PCICONF1_PBBE 0x00000200 /* Back 2 Back Control */ 68 #define SH7751_PCICONF1_SER 0x00000100 /* SERR Output Control */ 69 #define SH7751_PCICONF1_WCC 0x00000080 /* Wait Cycle Control */ 70 #define SH7751_PCICONF1_PER 0x00000040 /* Parity Error Response */ 71 #define SH7751_PCICONF1_VPS 0x00000020 /* VGA Pallet Snoop */ 72 #define SH7751_PCICONF1_MWIE 0x00000010 /* Memory Write+Invalidate */ 73 #define SH7751_PCICONF1_SPC 0x00000008 /* Special Cycle Control */ 74 #define SH7751_PCICONF1_BUM 0x00000004 /* Bus Master Control */ 75 #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */ 76 #define SH7751_PCICONF1_IOS 0x00000001 /* I/O Space Control */ 77 #define SH7751_PCICONF2 0x8 /* PCI Config Reg 2 */ 78 #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */ 79 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */ 80 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */ 81 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */ 82 #define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */ 83 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ 84 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ 85 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ 86 #define SH7751_PCICONF3_HD7 0x00800000 /* Single Funtion device */ 87 #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */ 88 #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */ 89 #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */ 90 #define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */ 91 #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */ 92 #define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */ 93 #define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */ 94 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 95 #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */ 96 #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */ 97 #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */ 98 #define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */ 99 #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 100 #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */ 101 #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */ 102 #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */ 103 /* PCICONF7 - PCICONF10 are undefined */ 104 #define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */ 105 #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */ 106 #define SH7751_PCICONF11_SVID 0x0000FFFF /* Subsystem Vendor ID */ 107 /* PCICONF12 is undefined */ 108 #define SH7751_PCICONF13 0x34 /* PCI Config Reg 13 */ 109 #define SH7751_PCICONF13_CPTR 0x000000FF /* PM function pointer */ 110 /* PCICONF14 is undefined */ 111 #define SH7751_PCICONF15 0x3C /* PCI Config Reg 15 */ 112 #define SH7751_PCICONF15_IPIN 0x000000FF /* Interrupt Pin */ 113 #define SH7751_PCICONF16 0x40 /* PCI Config Reg 16 */ 114 #define SH7751_PCICONF16_PMES 0xF8000000 /* PME Support */ 115 #define SH7751_PCICONF16_D2S 0x04000000 /* D2 Support */ 116 #define SH7751_PCICONF16_D1S 0x02000000 /* D1 Support */ 117 #define SH7751_PCICONF16_DSI 0x00200000 /* Bit Device Init. */ 118 #define SH7751_PCICONF16_PMCK 0x00080000 /* Clock for PME req. */ 119 #define SH7751_PCICONF16_VER 0x00070000 /* PM Version */ 120 #define SH7751_PCICONF16_NIP 0x0000FF00 /* Next Item Pointer */ 121 #define SH7751_PCICONF16_CID 0x000000FF /* Capability Identifier */ 122 #define SH7751_PCICONF17 0x44 /* PCI Config Reg 17 */ 123 #define SH7751_PCICONF17_DATA 0xFF000000 /* Data field for PM */ 124 #define SH7751_PCICONF17_PMES 0x00800000 /* PME Status */ 125 #define SH7751_PCICONF17_DSCL 0x00600000 /* Data Scaling Value */ 126 #define SH7751_PCICONF17_DSEL 0x001E0000 /* Data Select */ 127 #define SH7751_PCICONF17_PMEN 0x00010000 /* PME Enable */ 128 #define SH7751_PCICONF17_PWST 0x00000003 /* Power State */ 129 /* SH7715 Internal PCI Registers */ 130 #define SH7751_PCICR 0x100 /* PCI Control Register */ 131 #define SH7751_PCICR_PREFIX 0xA5000000 /* CR prefix for write */ 132 #define SH7751_PCICR_TRSB 0x00000200 /* Target Read Single */ 133 #define SH7751_PCICR_BSWP 0x00000100 /* Target Byte Swap */ 134 #define SH7751_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */ 135 #define SH7751_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */ 136 #define SH7751_PCICR_MD 0x00000030 /* MD9 and MD10 status */ 137 #define SH7751_PCICR_SERR 0x00000008 /* SERR output assert */ 138 #define SH7751_PCICR_INTA 0x00000004 /* INTA output assert */ 139 #define SH7751_PCICR_PRST 0x00000002 /* PCI Reset Assert */ 140 #define SH7751_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */ 141 #define SH7751_PCILSR0 0x104 /* PCI Local Space Register0 */ 142 #define SH7751_PCILSR1 0x108 /* PCI Local Space Register1 */ 143 #define SH7751_PCILAR0 0x10C /* PCI Local Address Register1 */ 144 #define SH7751_PCILAR1 0x110 /* PCI Local Address Register1 */ 145 #define SH7751_PCIINT 0x114 /* PCI Interrupt Register */ 146 #define SH7751_PCIINT_MLCK 0x00008000 /* Master Lock Error */ 147 #define SH7751_PCIINT_TABT 0x00004000 /* Target Abort Error */ 148 #define SH7751_PCIINT_TRET 0x00000200 /* Target Retry Error */ 149 #define SH7751_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */ 150 #define SH7751_PCIINT_PRTY 0x00000080 /* Address Parity Error */ 151 #define SH7751_PCIINT_SERR 0x00000040 /* SERR Detection Error */ 152 #define SH7751_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */ 153 #define SH7751_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Error Det. */ 154 #define SH7751_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */ 155 #define SH7751_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */ 156 #define SH7751_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */ 157 #define SH7751_PCIINT_MRPD 0x00000002 /* Master Read PERR Detect */ 158 #define SH7751_PCIINTM 0x118 /* PCI Interrupt Mask Register */ 159 #define SH7751_PCIALR 0x11C /* Error Address Register */ 160 #define SH7751_PCICLR 0x120 /* Error Command/Data Register */ 161 #define SH7751_PCICLR_MPIO 0x80000000 /* Error Command/Data Register */ 162 #define SH7751_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */ 163 #define SH7751_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */ 164 #define SH7751_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */ 165 #define SH7751_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */ 166 #define SH7751_PCICLR_TGT 0x04000000 /* Target Transfer Error */ 167 #define SH7751_PCICLR_CMDL 0x0000000F /* PCI Command at Error */ 168 #define SH7751_PCIAINT 0x130 /* Arbiter Interrupt Register */ 169 #define SH7751_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */ 170 #define SH7751_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */ 171 #define SH7751_PCIAINT_MBTO 0x00001000 /* Master Bus Time Out */ 172 #define SH7751_PCIAINT_TABT 0x00000008 /* Target Abort */ 173 #define SH7751_PCIAINT_MABT 0x00000004 /* Master Abort */ 174 #define SH7751_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */ 175 #define SH7751_PCIAINT_WDPE 0x00000002 /* Write Data Parity Error */ 176 #define SH7751_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ 177 #define SH7751_PCIBMLR 0x138 /* Error Bus Master Register */ 178 #define SH7751_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */ 179 #define SH7751_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */ 180 #define SH7751_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */ 181 #define SH7751_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */ 182 #define SH7751_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */ 183 #define SH7751_PCIDMABT 0x140 /* DMA Transfer Arb. Register */ 184 #define SH7751_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */ 185 #define SH7751_PCIDPA0 0x180 /* DMA0 Transfer Addr. Register */ 186 #define SH7751_PCIDLA0 0x184 /* DMA0 Local Addr. Register */ 187 #define SH7751_PCIDTC0 0x188 /* DMA0 Transfer Cnt. Register */ 188 #define SH7751_PCIDCR0 0x18C /* DMA0 Control Register */ 189 #define SH7751_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */ 190 #define SH7751_PCIDCR_MAST 0x00000100 /* DMA Termination Type */ 191 #define SH7751_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/ 192 #define SH7751_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */ 193 #define SH7751_PCIDCR_LHLD 0x00000020 /* Local Address Control */ 194 #define SH7751_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/ 195 #define SH7751_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */ 196 #define SH7751_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */ 197 #define SH7751_PCIDCR_STOP 0x00000002 /* Force DMA Stop */ 198 #define SH7751_PCIDCR_STRT 0x00000001 /* DMA Start */ 199 #define SH7751_PCIDPA1 0x190 /* DMA1 Transfer Addr. Register */ 200 #define SH7751_PCIDLA1 0x194 /* DMA1 Local Addr. Register */ 201 #define SH7751_PCIDTC1 0x198 /* DMA1 Transfer Cnt. Register */ 202 #define SH7751_PCIDCR1 0x19C /* DMA1 Control Register */ 203 #define SH7751_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. Register */ 204 #define SH7751_PCIDLA2 0x1A4 /* DMA2 Local Addr. Register */ 205 #define SH7751_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. Register */ 206 #define SH7751_PCIDCR2 0x1AC /* DMA2 Control Register */ 207 #define SH7751_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. Register */ 208 #define SH7751_PCIDLA3 0x1B4 /* DMA3 Local Addr. Register */ 209 #define SH7751_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. Register */ 210 #define SH7751_PCIDCR3 0x1BC /* DMA3 Control Register */ 211 #define SH7751_PCIPAR 0x1C0 /* PIO Address Register */ 212 #define SH7751_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */ 213 #define SH7751_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */ 214 #define SH7751_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */ 215 #define SH7751_PCIPAR_REGAD 0x000000FC /* Register Address Number */ 216 #define SH7751_PCIMBR 0x1C4 /* Memory Base Address Register */ 217 #define SH7751_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */ 218 #define SH7751_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */ 219 #define SH7751_PCIIOBR 0x1C8 /* I/O Base Address Register */ 220 #define SH7751_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */ 221 #define SH7751_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */ 222 #define SH7751_PCIPINT 0x1CC /* Power Mgmnt Int. Register */ 223 #define SH7751_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */ 224 #define SH7751_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */ 225 #define SH7751_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */ 226 #define SH7751_PCICLKR 0x1D4 /* Clock Ctrl. Register */ 227 #define SH7751_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */ 228 #define SH7751_PCICLKR_BCSTP 0x00000002 /* BCLK Clock Stop */ 229 /* For definitions of BCR, MCR see ... */ 230 #define SH7751_PCIBCR1 0x1E0 /* Memory BCR1 Register */ 231 #define SH7751_PCIBCR2 0x1E4 /* Memory BCR2 Register */ 232 #define SH7751_PCIWCR1 0x1E8 /* Wait Control 1 Register */ 233 #define SH7751_PCIWCR2 0x1EC /* Wait Control 2 Register */ 234 #define SH7751_PCIWCR3 0x1F0 /* Wait Control 3 Register */ 235 #define SH7751_PCIMCR 0x1F4 /* Memory Control Register */ 236 #define SH7751_PCIPCTR 0x200 /* Port Control Register */ 237 #define SH7751_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */ 238 #define SH7751_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */ 239 #define SH7751_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */ 240 #define SH7751_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */ 241 #define SH7751_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */ 242 #define SH7751_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */ 243 #define SH7751_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */ 244 #define SH7751_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */ 245 #define SH7751_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */ 246 #define SH7751_PCIPDTR 0x204 /* Port Data Register */ 247 #define SH7751_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */ 248 #define SH7751_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */ 249 #define SH7751_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */ 250 #define SH7751_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */ 251 #define SH7751_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */ 252 #define SH7751_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */ 253 #define SH7751_PCIPDR 0x220 /* Port IO Data Register */ 254 255 /* Memory Control Registers */ 256 #define SH7751_BCR1 0xFF800000 /* Memory BCR1 Register */ 257 #define SH7751_BCR2 0xFF800004 /* Memory BCR2 Register */ 258 #define SH7751_WCR1 0xFF800008 /* Wait Control 1 Register */ 259 #define SH7751_WCR2 0xFF80000C /* Wait Control 2 Register */ 260 #define SH7751_WCR3 0xFF800010 /* Wait Control 3 Register */ 261 #define SH7751_MCR 0xFF800014 /* Memory Control Register */ 262 263 /* General Memory Config Addresses */ 264 #define SH7751_CS0_BASE_ADDR 0x0 265 #define SH7751_MEM_REGION_SIZE 0x04000000 266 #define SH7751_CS1_BASE_ADDR (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE) 267 #define SH7751_CS2_BASE_ADDR (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE) 268 #define SH7751_CS3_BASE_ADDR (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE) 269 #define SH7751_CS4_BASE_ADDR (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE) 270 #define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE) 271 #define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE) 272 273 /* General PCI values */ 274 #define SH7751_PCI_HOST_BRIDGE 0x6 275 276 /* External functions defined per platform i.e. Big Sur, SE... (these could be routed 277 * through the machine vectors... */ 278 extern int pcibios_init_platform(void); 279 extern int pcibios_map_platform_irq(u8 slot, u8 pin); 280 281 #endif /* _PCI_SH7751_H_ */ 282 283