1 #ifndef __ASM_SH_DMA_H
2 #define __ASM_SH_DMA_H
3
4 #include <linux/config.h>
5 #include <asm/io.h> /* need byte IO */
6
7 #define MAX_DMA_CHANNELS 8
8 #define SH_MAX_DMA_CHANNELS 4
9
10 /* The maximum address that we can perform a DMA transfer to on this platform */
11 /* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
12 occurrence should be flagged as an error. */
13 /* But... */
14 /* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
15 #define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
16
17 #if defined(__sh3__)
18 #define SAR ((unsigned long[]){0xa4000020,0xa4000030,0xa4000040,0xa4000050})
19 #define DAR ((unsigned long[]){0xa4000024,0xa4000034,0xa4000044,0xa4000054})
20 #define DMATCR ((unsigned long[]){0xa4000028,0xa4000038,0xa4000048,0xa4000058})
21 #define CHCR ((unsigned long[]){0xa400002c,0xa400003c,0xa400004c,0xa400005c})
22 #define DMAOR 0xa4000060UL
23 #elif defined(__SH4__)
24 #define SAR ((unsigned long[]){0xbfa00000,0xbfa00010,0xbfa00020,0xbfa00030})
25 #define DAR ((unsigned long[]){0xbfa00004,0xbfa00014,0xbfa00024,0xbfa00034})
26 #define DMATCR ((unsigned long[]){0xbfa00008,0xbfa00018,0xbfa00028,0xbfa00038})
27 #define CHCR ((unsigned long[]){0xbfa0000c,0xbfa0001c,0xbfa0002c,0xbfa0003c})
28 #define DMAOR 0xbfa00040UL
29 #endif
30
31 #define DMTE_IRQ ((int[]){DMTE0_IRQ,DMTE1_IRQ,DMTE2_IRQ,DMTE3_IRQ})
32
33 #define DMA_MODE_READ 0x00 /* I/O to memory, no autoinit, increment, single mode */
34 #define DMA_MODE_WRITE 0x01 /* memory to I/O, no autoinit, increment, single mode */
35 #define DMA_AUTOINIT 0x10
36
37 #define REQ_L 0x00000000
38 #define REQ_E 0x00080000
39 #define RACK_H 0x00000000
40 #define RACK_L 0x00040000
41 #define ACK_R 0x00000000
42 #define ACK_W 0x00020000
43 #define ACK_H 0x00000000
44 #define ACK_L 0x00010000
45 #define DM_INC 0x00004000
46 #define DM_DEC 0x00008000
47 #define SM_INC 0x00001000
48 #define SM_DEC 0x00002000
49 #define RS_DUAL 0x00000000
50 #define RS_IN 0x00000200
51 #define RS_OUT 0x00000300
52 #define TM_BURST 0x0000080
53 #define TS_8 0x00000010
54 #define TS_16 0x00000020
55 #define TS_32 0x00000030
56 #define TS_64 0x00000000
57 #define TS_BLK 0x00000040
58 #define CHCR_DE 0x00000001
59 #define CHCR_TE 0x00000002
60 #define CHCR_IE 0x00000004
61
62 #define DMAOR_COD 0x00000008
63 #define DMAOR_AE 0x00000004
64 #define DMAOR_NMIF 0x00000002
65 #define DMAOR_DME 0x00000001
66
67 struct dma_info_t {
68 unsigned int chan;
69 unsigned int mode_read;
70 unsigned int mode_write;
71 unsigned long dev_addr;
72 unsigned int mode;
73 unsigned long mem_addr;
74 unsigned int count;
75 };
76
clear_dma_ff(unsigned int dmanr)77 static __inline__ void clear_dma_ff(unsigned int dmanr){}
78
79 /* These are in arch/sh/kernel/dma.c: */
80 extern unsigned long claim_dma_lock(void);
81 extern void release_dma_lock(unsigned long flags);
82 extern void setup_dma(unsigned int dmanr, struct dma_info_t *info);
83 extern void enable_dma(unsigned int dmanr);
84 extern void disable_dma(unsigned int dmanr);
85 extern void set_dma_mode(unsigned int dmanr, char mode);
86 extern void set_dma_addr(unsigned int dmanr, unsigned int a);
87 extern void set_dma_count(unsigned int dmanr, unsigned int count);
88 extern int get_dma_residue(unsigned int dmanr);
89
90 #ifdef CONFIG_PCI
91 extern int isa_dma_bridge_buggy;
92 #else
93 #define isa_dma_bridge_buggy (0)
94 #endif
95
96
97 #endif /* __ASM_SH_DMA_H */
98