1 /*
2 * include/asm-s390/smp.h
3 *
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 */
9 #ifndef __ASM_SMP_H
10 #define __ASM_SMP_H
11
12 #include <linux/config.h>
13
14 #if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
15
16 #include <asm/lowcore.h>
17
18 /*
19 s390 specific smp.c headers
20 */
21 typedef struct
22 {
23 int intresting;
24 sigp_ccode ccode;
25 __u32 status;
26 __u16 cpu;
27 } sigp_info;
28
29 extern int smp_call_function_on(void (*func) (void *info), void *info,
30 int nonatomic, int wait, int cpu);
31
32 extern unsigned long cpu_online_map;
33
34 #define NO_PROC_ID 0xFF /* No processor magic marker */
35
36 /*
37 * This magic constant controls our willingness to transfer
38 * a process across CPUs. Such a transfer incurs misses on the L1
39 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
40 * gut feeling is this will vary by board in value. For a board
41 * with separate L2 cache it probably depends also on the RSS, and
42 * for a board with shared L2 cache it ought to decay fast as other
43 * processes are run.
44 */
45
46 #define PROC_CHANGE_PENALTY 20 /* Schedule penalty */
47
48 #define smp_processor_id() (current->processor)
49
cpu_logical_map(int cpu)50 extern __inline__ int cpu_logical_map(int cpu)
51 {
52 return cpu;
53 }
54
cpu_number_map(int cpu)55 extern __inline__ int cpu_number_map(int cpu)
56 {
57 return cpu;
58 }
59
hard_smp_processor_id(void)60 extern __inline__ __u16 hard_smp_processor_id(void)
61 {
62 __u16 cpu_address;
63
64 __asm__ ("stap %0\n" : "=m" (cpu_address));
65 return cpu_address;
66 }
67
68 #define cpu_logical_map(cpu) (cpu)
69
70 #endif
71
72 #ifndef CONFIG_SMP
73 #define smp_call_function_on(func,info,nonatomic,wait,cpu) ({ 0; })
74 #endif
75
76 #endif
77