1 /* 2 * arch/ppc/kernel/pplus.h 3 * 4 * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. 5 * 6 * Author: Mark A. Greer 7 * mgreer@mvista.com 8 * 9 * Copyright 2001 MontaVista Software Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17 #ifndef __ASMPPC_PPLUS_H 18 #define __ASMPPC_PPLUS_H 19 20 #include <asm/pci-bridge.h> 21 22 /* 23 * The Falcon/Raven and HAWK have 4 sets of registers: 24 * 1) PPC Registers which define the mappings from PPC bus to PCI bus, 25 * etc. 26 * 2) PCI Registers which define the mappings from PCI bus to PPC bus and the 27 * MPIC base address. 28 * 3) MPIC registers 29 * 4) System Memory Controller (SMC) registers. 30 */ 31 32 #define PPLUS_RAVEN_VEND_DEV_ID 0x48011057 33 #define PPLUS_HAWK_VEND_DEV_ID 0x48031057 34 35 #define PPLUS_PCI_CONFIG_ADDR_OFF 0x00000cf8 36 #define PPLUS_PCI_CONFIG_DATA_OFF 0x00000cfc 37 38 #define PPLUS_MPIC_SIZE 0x00040000U 39 #define PPLUS_SMC_SIZE 0x00001000U 40 41 /* 42 * Define PPC register offsets. 43 */ 44 #define PPLUS_PPC_XSADD0_OFF 0x40 45 #define PPLUS_PPC_XSOFF0_OFF 0x44 46 #define PPLUS_PPC_XSADD1_OFF 0x48 47 #define PPLUS_PPC_XSOFF1_OFF 0x4c 48 #define PPLUS_PPC_XSADD2_OFF 0x50 49 #define PPLUS_PPC_XSOFF2_OFF 0x54 50 #define PPLUS_PPC_XSADD3_OFF 0x58 51 #define PPLUS_PPC_XSOFF3_OFF 0x5c 52 53 /* 54 * Define PCI register offsets. 55 */ 56 #define PPLUS_PCI_PSADD0_OFF 0x80 57 #define PPLUS_PCI_PSOFF0_OFF 0x84 58 #define PPLUS_PCI_PSADD1_OFF 0x88 59 #define PPLUS_PCI_PSOFF1_OFF 0x8c 60 #define PPLUS_PCI_PSADD2_OFF 0x90 61 #define PPLUS_PCI_PSOFF2_OFF 0x94 62 #define PPLUS_PCI_PSADD3_OFF 0x98 63 #define PPLUS_PCI_PSOFF3_OFF 0x9c 64 65 /* 66 * Define the System Memory Controller (SMC) register offsets. 67 */ 68 #define PPLUS_SMC_RAM_A_SIZE_REG_OFF 0x10 69 #define PPLUS_SMC_RAM_B_SIZE_REG_OFF 0x11 70 #define PPLUS_SMC_RAM_C_SIZE_REG_OFF 0x12 71 #define PPLUS_SMC_RAM_D_SIZE_REG_OFF 0x13 72 #define PPLUS_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */ 73 #define PPLUS_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */ 74 #define PPLUS_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */ 75 #define PPLUS_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */ 76 77 #define PPLUS_FALCON_SMC_REG_COUNT 4 78 #define PPLUS_HAWK_SMC_REG_COUNT 8 79 80 81 82 int pplus_init(struct pci_controller *hose, 83 uint ppc_reg_base, 84 ulong processor_pci_mem_start, 85 ulong processor_pci_mem_end, 86 ulong processor_pci_io_start, 87 ulong processor_pci_io_end, 88 ulong processor_mpic_base); 89 90 unsigned long pplus_get_mem_size(uint smc_base); 91 92 int pplus_mpic_init(unsigned int pci_mem_offset); 93 94 #endif /* __ASMPPC_PPLUS_H */ 95