1 /* 2 * include/asm-ppc/ppc_asm.h 3 * 4 * Definitions used by various bits of low-level assembly code on PowerPC. 5 * 6 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 #include <linux/config.h> 15 16 /* 17 * Macros for storing registers into and loading registers from 18 * exception frames. 19 */ 20 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 21 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 22 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 23 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 24 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 25 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 26 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 27 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 28 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 29 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 30 31 #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base) 32 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 33 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 34 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 35 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 36 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 37 #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base) 38 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 39 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 40 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 41 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 42 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 43 44 /* 45 * Once a version of gas that understands the AltiVec instructions 46 * is freely available, we can do this the normal way... - paulus 47 */ 48 #define LVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(103<<1) 49 #define STVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(231<<1) 50 #define MFVSCR(r) .long (4<<26)+((r)<<21)+(770<<1) 51 #define MTVSCR(r) .long (4<<26)+((r)<<11)+(802<<1) 52 #define DSSALL .long (0x1f<<26)+(0x10<<21)+(0x336<<1) 53 54 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); STVX(n,b,base) 55 #define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 56 #define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base) 57 #define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base) 58 #define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base) 59 #define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base) 60 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); LVX(n,b,base) 61 #define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 62 #define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base) 63 #define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base) 64 #define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base) 65 #define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base) 66 67 #ifdef CONFIG_PPC601_SYNC_FIX 68 #define SYNC \ 69 BEGIN_FTR_SECTION \ 70 sync; \ 71 isync; \ 72 END_FTR_SECTION_IFSET(CPU_FTR_601) 73 #define SYNC_601 \ 74 BEGIN_FTR_SECTION \ 75 sync; \ 76 END_FTR_SECTION_IFSET(CPU_FTR_601) 77 #define ISYNC_601 \ 78 BEGIN_FTR_SECTION \ 79 isync; \ 80 END_FTR_SECTION_IFSET(CPU_FTR_601) 81 #else 82 #define SYNC 83 #define SYNC_601 84 #define ISYNC_601 85 #endif 86 87 #ifndef CONFIG_SMP 88 #define TLBSYNC 89 #else /* CONFIG_SMP */ 90 /* tlbsync is not implemented on 601 */ 91 #define TLBSYNC \ 92 BEGIN_FTR_SECTION \ 93 tlbsync; \ 94 sync; \ 95 END_FTR_SECTION_IFCLR(CPU_FTR_601) 96 #endif 97 98 /* 99 * This instruction is not implemented on the PPC 603 or 601; however, on 100 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 101 * All of these instructions exist in the 8xx, they have magical powers, 102 * and they must be used. 103 */ 104 105 #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 106 #define tlbia \ 107 li r4,1024; \ 108 mtctr r4; \ 109 lis r4,KERNELBASE@h; \ 110 0: tlbie r4; \ 111 addi r4,r4,0x1000; \ 112 bdnz 0b 113 #endif 114 115 #ifdef CONFIG_BOOKE 116 #define tophys(rd,rs) \ 117 mr rd,rs 118 #define tovirt(rd,rs) \ 119 mr rd,rs 120 #else /* CONFIG_BOOKE */ 121 /* 122 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 123 * physical base address of RAM at compile time. 124 */ 125 #define tophys(rd,rs) \ 126 0: addis rd,rs,-KERNELBASE@h; \ 127 .section ".vtop_fixup","aw"; \ 128 .align 1; \ 129 .long 0b; \ 130 .previous 131 132 #define tovirt(rd,rs) \ 133 0: addis rd,rs,KERNELBASE@h; \ 134 .section ".ptov_fixup","aw"; \ 135 .align 1; \ 136 .long 0b; \ 137 .previous 138 #endif /* CONFIG_BOOKE */ 139 140 /* 141 * On 64-bit cpus, we use the rfid instruction instead of rfi, but 142 * we then have to make sure we preserve the top 32 bits except for 143 * the 64-bit mode bit, which we clear. 144 */ 145 #ifdef CONFIG_PPC64BRIDGE 146 #define FIX_SRR1(ra, rb) \ 147 mr rb,ra; \ 148 mfmsr ra; \ 149 clrldi ra,ra,1; /* turn off 64-bit mode */ \ 150 rldimi ra,rb,0,32 151 #define RFI .long 0x4c000024 /* rfid instruction */ 152 #define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */ 153 #define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */ 154 155 #else 156 #define FIX_SRR1(ra, rb) 157 #ifndef CONFIG_4xx 158 #define RFI rfi 159 #else 160 #define RFI rfi; b . /* prevent prefetch past rfi */ 161 #endif 162 #define MTMSRD(r) mtmsr r 163 #define CLR_TOP32(r) 164 #endif /* CONFIG_PPC64BRIDGE */ 165 166 #define RFMCI .long 0x4c00004c /* rfmci instruction */ 167 168 #ifdef CONFIG_IBM405_ERR77 169 #define PPC405_ERR77(ra,rb) dcbt ra, rb; 170 #define PPC405_ERR77_SYNC sync; 171 #else 172 #define PPC405_ERR77(ra,rb) 173 #define PPC405_ERR77_SYNC 174 #endif 175 176 /* The boring bits... */ 177 178 /* Condition Register Bit Fields */ 179 180 #define cr0 0 181 #define cr1 1 182 #define cr2 2 183 #define cr3 3 184 #define cr4 4 185 #define cr5 5 186 #define cr6 6 187 #define cr7 7 188 189 190 /* General Purpose Registers (GPRs) */ 191 192 #define r0 0 193 #define r1 1 194 #define r2 2 195 #define r3 3 196 #define r4 4 197 #define r5 5 198 #define r6 6 199 #define r7 7 200 #define r8 8 201 #define r9 9 202 #define r10 10 203 #define r11 11 204 #define r12 12 205 #define r13 13 206 #define r14 14 207 #define r15 15 208 #define r16 16 209 #define r17 17 210 #define r18 18 211 #define r19 19 212 #define r20 20 213 #define r21 21 214 #define r22 22 215 #define r23 23 216 #define r24 24 217 #define r25 25 218 #define r26 26 219 #define r27 27 220 #define r28 28 221 #define r29 29 222 #define r30 30 223 #define r31 31 224 225 226 /* Floating Point Registers (FPRs) */ 227 228 #define fr0 0 229 #define fr1 1 230 #define fr2 2 231 #define fr3 3 232 #define fr4 4 233 #define fr5 5 234 #define fr6 6 235 #define fr7 7 236 #define fr8 8 237 #define fr9 9 238 #define fr10 10 239 #define fr11 11 240 #define fr12 12 241 #define fr13 13 242 #define fr14 14 243 #define fr15 15 244 #define fr16 16 245 #define fr17 17 246 #define fr18 18 247 #define fr19 19 248 #define fr20 20 249 #define fr21 21 250 #define fr22 22 251 #define fr23 23 252 #define fr24 24 253 #define fr25 25 254 #define fr26 26 255 #define fr27 27 256 #define fr28 28 257 #define fr29 29 258 #define fr30 30 259 #define fr31 31 260 261 #define vr0 0 262 #define vr1 1 263 #define vr2 2 264 #define vr3 3 265 #define vr4 4 266 #define vr5 5 267 #define vr6 6 268 #define vr7 7 269 #define vr8 8 270 #define vr9 9 271 #define vr10 10 272 #define vr11 11 273 #define vr12 12 274 #define vr13 13 275 #define vr14 14 276 #define vr15 15 277 #define vr16 16 278 #define vr17 17 279 #define vr18 18 280 #define vr19 19 281 #define vr20 20 282 #define vr21 21 283 #define vr22 22 284 #define vr23 23 285 #define vr24 24 286 #define vr25 25 287 #define vr26 26 288 #define vr27 27 289 #define vr28 28 290 #define vr29 29 291 #define vr30 30 292 #define vr31 31 293 294 /* some stab codes */ 295 #define N_FUN 36 296 #define N_RSYM 64 297 #define N_SLINE 68 298 #define N_SO 100 299