1 /*
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 * Changes for ppc sound by Christoph Nadig
7 */
8
9 #ifdef __KERNEL__
10
11 #include <linux/config.h>
12 #include <asm/io.h>
13 #include <linux/spinlock.h>
14 #include <asm/system.h>
15
16 /*
17 * Note: Adapted for PowerPC by Gary Thomas
18 * Modified by Cort Dougan <cort@cs.nmt.edu>
19 *
20 * None of this really applies for Power Macintoshes. There is
21 * basically just enough here to get kernel/dma.c to compile.
22 *
23 * There may be some comments or restrictions made here which are
24 * not valid for the PReP platform. Take what you read
25 * with a grain of salt.
26 */
27
28
29 #ifndef _ASM_DMA_H
30 #define _ASM_DMA_H
31
32 #ifndef MAX_DMA_CHANNELS
33 #define MAX_DMA_CHANNELS 8
34 #endif
35
36 /* The maximum address that we can perform a DMA transfer to on this platform */
37 /* Doesn't really apply... */
38 #define MAX_DMA_ADDRESS 0xFFFFFFFF
39
40 /* in arch/ppc/kernel/setup.c -- Cort */
41 extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
42 extern unsigned long ISA_DMA_THRESHOLD;
43
44 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
45 #define dma_outb outb_p
46 #else
47 #define dma_outb outb
48 #endif
49
50 #define dma_inb inb
51
52 /*
53 * NOTES about DMA transfers:
54 *
55 * controller 1: channels 0-3, byte operations, ports 00-1F
56 * controller 2: channels 4-7, word operations, ports C0-DF
57 *
58 * - ALL registers are 8 bits only, regardless of transfer size
59 * - channel 4 is not used - cascades 1 into 2.
60 * - channels 0-3 are byte - addresses/counts are for physical bytes
61 * - channels 5-7 are word - addresses/counts are for physical words
62 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
63 * - transfer count loaded to registers is 1 less than actual count
64 * - controller 2 offsets are all even (2x offsets for controller 1)
65 * - page registers for 5-7 don't use data bit 0, represent 128K pages
66 * - page registers for 0-3 use bit 0, represent 64K pages
67 *
68 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
69 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
70 * Note that addresses loaded into registers must be _physical_ addresses,
71 * not logical addresses (which may differ if paging is active).
72 *
73 * Address mapping for channels 0-3:
74 *
75 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
76 * | ... | | ... | | ... |
77 * | ... | | ... | | ... |
78 * | ... | | ... | | ... |
79 * P7 ... P0 A7 ... A0 A7 ... A0
80 * | Page | Addr MSB | Addr LSB | (DMA registers)
81 *
82 * Address mapping for channels 5-7:
83 *
84 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
85 * | ... | \ \ ... \ \ \ ... \ \
86 * | ... | \ \ ... \ \ \ ... \ (not used)
87 * | ... | \ \ ... \ \ \ ... \
88 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
89 * | Page | Addr MSB | Addr LSB | (DMA registers)
90 *
91 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
92 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
93 * the hardware level, so odd-byte transfers aren't possible).
94 *
95 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
96 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
97 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
98 *
99 */
100
101 /* see prep_setup_arch() for detailed informations */
102 #if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_ALL_PPC)
103 extern long ppc_cs4232_dma, ppc_cs4232_dma2;
104 #define SND_DMA1 ppc_cs4232_dma
105 #define SND_DMA2 ppc_cs4232_dma2
106 #else
107 #define SND_DMA1 -1
108 #define SND_DMA2 -1
109 #endif
110
111 /* 8237 DMA controllers */
112 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
113 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
114
115 /* DMA controller registers */
116 #define DMA1_CMD_REG 0x08 /* command register (w) */
117 #define DMA1_STAT_REG 0x08 /* status register (r) */
118 #define DMA1_REQ_REG 0x09 /* request register (w) */
119 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
120 #define DMA1_MODE_REG 0x0B /* mode register (w) */
121 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
122 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
123 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
124 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
125 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
126
127 #define DMA2_CMD_REG 0xD0 /* command register (w) */
128 #define DMA2_STAT_REG 0xD0 /* status register (r) */
129 #define DMA2_REQ_REG 0xD2 /* request register (w) */
130 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
131 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
132 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
133 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
134 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
135 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
136 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
137
138 #define DMA_ADDR_0 0x00 /* DMA address registers */
139 #define DMA_ADDR_1 0x02
140 #define DMA_ADDR_2 0x04
141 #define DMA_ADDR_3 0x06
142 #define DMA_ADDR_4 0xC0
143 #define DMA_ADDR_5 0xC4
144 #define DMA_ADDR_6 0xC8
145 #define DMA_ADDR_7 0xCC
146
147 #define DMA_CNT_0 0x01 /* DMA count registers */
148 #define DMA_CNT_1 0x03
149 #define DMA_CNT_2 0x05
150 #define DMA_CNT_3 0x07
151 #define DMA_CNT_4 0xC2
152 #define DMA_CNT_5 0xC6
153 #define DMA_CNT_6 0xCA
154 #define DMA_CNT_7 0xCE
155
156 #define DMA_LO_PAGE_0 0x87 /* DMA page registers */
157 #define DMA_LO_PAGE_1 0x83
158 #define DMA_LO_PAGE_2 0x81
159 #define DMA_LO_PAGE_3 0x82
160 #define DMA_LO_PAGE_5 0x8B
161 #define DMA_LO_PAGE_6 0x89
162 #define DMA_LO_PAGE_7 0x8A
163
164 #define DMA_HI_PAGE_0 0x487 /* DMA page registers */
165 #define DMA_HI_PAGE_1 0x483
166 #define DMA_HI_PAGE_2 0x481
167 #define DMA_HI_PAGE_3 0x482
168 #define DMA_HI_PAGE_5 0x48B
169 #define DMA_HI_PAGE_6 0x489
170 #define DMA_HI_PAGE_7 0x48A
171
172 #define DMA1_EXT_REG 0x40B
173 #define DMA2_EXT_REG 0x4D6
174
175 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
176 #define DMA_AUTOINIT 0x10
177
178 extern spinlock_t dma_spin_lock;
179
claim_dma_lock(void)180 static __inline__ unsigned long claim_dma_lock(void)
181 {
182 unsigned long flags;
183 spin_lock_irqsave(&dma_spin_lock, flags);
184 return flags;
185 }
186
release_dma_lock(unsigned long flags)187 static __inline__ void release_dma_lock(unsigned long flags)
188 {
189 spin_unlock_irqrestore(&dma_spin_lock, flags);
190 }
191
192 /* enable/disable a specific DMA channel */
enable_dma(unsigned int dmanr)193 static __inline__ void enable_dma(unsigned int dmanr)
194 {
195 unsigned char ucDmaCmd=0x00;
196
197 if (dmanr != 4) {
198 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
199 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
200 }
201 if (dmanr <= 3) {
202 dma_outb(dmanr, DMA1_MASK_REG);
203 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
204 } else
205 dma_outb(dmanr & 3, DMA2_MASK_REG);
206 }
207
disable_dma(unsigned int dmanr)208 static __inline__ void disable_dma(unsigned int dmanr)
209 {
210 if (dmanr <= 3)
211 dma_outb(dmanr | 4, DMA1_MASK_REG);
212 else
213 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
214 }
215
216 /* Clear the 'DMA Pointer Flip Flop'.
217 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
218 * Use this once to initialize the FF to a known state.
219 * After that, keep track of it. :-)
220 * --- In order to do that, the DMA routines below should ---
221 * --- only be used while interrupts are disabled! ---
222 */
clear_dma_ff(unsigned int dmanr)223 static __inline__ void clear_dma_ff(unsigned int dmanr)
224 {
225 if (dmanr <= 3)
226 dma_outb(0, DMA1_CLEAR_FF_REG);
227 else
228 dma_outb(0, DMA2_CLEAR_FF_REG);
229 }
230
231 /* set mode (above) for a specific DMA channel */
set_dma_mode(unsigned int dmanr,char mode)232 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
233 {
234 if (dmanr <= 3)
235 dma_outb(mode | dmanr, DMA1_MODE_REG);
236 else
237 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
238 }
239
240 /* Set only the page register bits of the transfer address.
241 * This is used for successive transfers when we know the contents of
242 * the lower 16 bits of the DMA current address register, but a 64k boundary
243 * may have been crossed.
244 */
set_dma_page(unsigned int dmanr,int pagenr)245 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
246 {
247 switch(dmanr) {
248 case 0:
249 dma_outb(pagenr, DMA_LO_PAGE_0);
250 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
251 break;
252 case 1:
253 dma_outb(pagenr, DMA_LO_PAGE_1);
254 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
255 break;
256 case 2:
257 dma_outb(pagenr, DMA_LO_PAGE_2);
258 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
259 break;
260 case 3:
261 dma_outb(pagenr, DMA_LO_PAGE_3);
262 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
263 break;
264 case 5:
265 if (SND_DMA1 == 5 || SND_DMA2 == 5)
266 dma_outb(pagenr, DMA_LO_PAGE_5);
267 else
268 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
269 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
270 break;
271 case 6:
272 if (SND_DMA1 == 6 || SND_DMA2 == 6)
273 dma_outb(pagenr, DMA_LO_PAGE_6);
274 else
275 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
276 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
277 break;
278 case 7:
279 if (SND_DMA1 == 7 || SND_DMA2 == 7)
280 dma_outb(pagenr, DMA_LO_PAGE_7);
281 else
282 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
283 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
284 break;
285 }
286 }
287
288
289 /* Set transfer address & page bits for specific DMA channel.
290 * Assumes dma flipflop is clear.
291 */
set_dma_addr(unsigned int dmanr,unsigned int phys)292 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
293 {
294 if (dmanr <= 3) {
295 dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE );
296 dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
297 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
298 dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE );
299 dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) +
300 IO_DMA2_BASE);
301 dma_outb((dmanr & 3), DMA2_EXT_REG);
302 } else {
303 dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
304 dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
305 }
306 set_dma_page(dmanr, phys >> 16);
307 }
308
309
310 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
311 * a specific DMA channel.
312 * You must ensure the parameters are valid.
313 * NOTE: from a manual: "the number of transfers is one more
314 * than the initial word count"! This is taken into account.
315 * Assumes dma flip-flop is clear.
316 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
317 */
set_dma_count(unsigned int dmanr,unsigned int count)318 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
319 {
320 count--;
321 if (dmanr <= 3) {
322 dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
323 dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 +
324 IO_DMA1_BASE);
325 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
326 dma_outb( count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
327 dma_outb( (count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 +
328 IO_DMA2_BASE);
329 } else {
330 dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 +
331 IO_DMA2_BASE);
332 dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 +
333 IO_DMA2_BASE);
334 }
335 }
336
337 /* Get DMA residue count. After a DMA transfer, this
338 * should return zero. Reading this while a DMA transfer is
339 * still in progress will return unpredictable results.
340 * If called before the channel has been used, it may return 1.
341 * Otherwise, it returns the number of _bytes_ left to transfer.
342 *
343 * Assumes DMA flip-flop is clear.
344 */
get_dma_residue(unsigned int dmanr)345 static __inline__ int get_dma_residue(unsigned int dmanr)
346 {
347 unsigned int io_port = (dmanr <= 3) ?
348 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
349 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
350
351 /* using short to get 16-bit wrap around */
352 unsigned short count;
353
354 count = 1 + dma_inb(io_port);
355 count += dma_inb(io_port) << 8;
356
357 return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
358 ? count : (count<<1);
359
360 }
361
362 /* These are in kernel/dma.c: */
363
364 /* reserve a DMA channel */
365 extern int request_dma(unsigned int dmanr, const char * device_id);
366 /* release it again */
367 extern void free_dma(unsigned int dmanr);
368
369 #ifdef CONFIG_PCI
370 extern int isa_dma_bridge_buggy;
371 #else
372 #define isa_dma_bridge_buggy (0)
373 #endif
374 #endif /* _ASM_DMA_H */
375 #endif /* __KERNEL__ */
376